bemicro cv, nios II, c

[Altera_Forum]

I'm pretty sure I bit off more than I can chew, but I'm not willing to give up yet. 

 The class is really about compiler optimization. You pick up the IR spit out by LLVM and optimize it and hand it off to whatever backend you're using and then test to see if you made it better or worse -- pretty simple really. For whatever reason, I wanted to try to optimize for space and parallelizm in FPGA, so I picked a board at random (BeMicro CV) and ordered one and then started trying to figure out Quartus, Qsys, Nios II ... I'm having trouble figuring out what any of these tools really are, though I've had some success getting LEDs to blink and pins to spit out serial and so forth.  I'm under the impression Nios II is a library/layout/program that runs on the fpga. Do I have this much right? And I'm further under the impression that the BeMicro CV can run this (mainly because of this: https://github.com/tommythorn/bemicro-cv/tree/master/nios_ddr3). Is this right?  I'm wondering if I can use clang (or a similar llvm compiler, of which there seem to be a few choices) to compile IR, *do my class project here*, then compile the IR to fpga using quartus/eds/etc and monitor the serials for program outputs on the BeMicro CV. Is this possible? Maybe use one of the various llvm2verilog compilers I'm finding? There's so much documentation on this site, I vacillate about whether I need 64 gigs of ram and a $5000 dev kit with a stratix pcie board or if I can do something really trivial on my little $50 board. It seems to me I can get something to work, but if I need to give up, it's better to know that this week rather than next week as a semester is only just so long.  (I'm not afraid to read docs, I'm just not sure where to dig in.)

[Altera_Forum]

You might be better looking at gcc, the niosII port sources can be downloaded from the altera web site (see the wiki), and have the build instructions. 

If you avoid all of libc then programs can be very small, but you need to do some 'hacking' to get rid of everythimg, the Altera 'BSP' objects end up needing malloc and free.

[Altera_Forum]

My suggestion would be to start here and the suggested Follow-On Courses 

http://www.altera.com/education/training/courses/oqsys1000  a) NIOS is a 32-bit microprocessor IP core b) Qsys is the tool you use to chain together IP cores and specify a system c) Quartus translates the Qsys output into an FPGA image you can program in your board. d) After your image is in your board, you use gcc/g++/gdb/Eclipse/yourcreation to execute software in the NIOS you put in your FPGA.  As far as purchases go, you can get quite far with the board you have chosen and whatever computer you already have.

[Altera_Forum]

--- Quote Start ---  My suggestion would be to start here and the suggested Follow-On Courses http://www.altera.com/education/training/courses/oqsys1000  a) NIOS is a 32-bit microprocessor IP core b) Qsys is the tool you use to chain together IP cores and specify a system c) Quartus translates the Qsys output into an FPGA image you can program in your board. d) After your image is in your board, you use gcc/g++/gdb/Eclipse/yourcreation to execute software in the NIOS you put in your FPGA.  As far as purchases go, you can get quite far with the board you have chosen and whatever computer you already have.  --- Quote End ---    Ted,  For such a simple post, this goes miles and miles for me. Thanks a lot. It's hard to see what these pieces do until you spend an hour or two with them. But this at least gives me an approach to get to the point that I can *start* my class project. If I can just get one or two simple things to feed from Eclipse to the NIOS mp core (I think I said that right) I can get this project done in time for sure.  I tried one of those courses to kinda learn the Quartus interfaces. I wish they weren't lecture format. I could read the entire text of the course in 40 minutes, but the lecture I selected was like 8 hours long and the information was parcele out rather slowly. I suppose if I can't immediately figure out what I'm doing I'll just have to commit the time to it. It's not the worst thing because I at least know I'm probably on the right track now.  Thanks again.

[Altera_Forum]

Ted, 

 This answer goes miles and miles for me. It's hard to see what these pieces do until you spend an hour or two with them. But this at least gives me an approach to get to the point that I can *start* my class project. If I can just get one or two simple things to feed from Eclipse to the NIOS mp core (I think I said that right) I can get this project done in time for sure.  I tried one of those courses to kinda learn the Quartus interfaces. I wish they weren't lecture format. I could read the entire text of the course in 40 minutes, but the lecture I selected was like 8 hours long and the information was parceled out rather slowly. I suppose if I can't immediately figure out what I'm doing I'll just have to commit the time to it. It's not the worst thing because I at least know I'm probably on the right track now.  Thanks again.

[Altera_Forum]

You do need to find a working qsys+nios project for your card. 

Trying to generate one from scratch is probably too hard....

[Altera_Forum]

--- Quote Start ---   d) After your image is in your board, you use gcc/g++/gdb/Eclipse/yourcreation to execute software in the NIOS you put in your FPGA.  --- Quote End ---     You know, it only took a couple hours to figure out …    --- Quote Start ---   Hello from Nios II!   --- Quote End ---    I mean, I cheated and used a template … but they make this all really simple if I newb can figure it out in an evening.  I wonder how (or if) I can inject llvm instead of gcc. I suppose I'm just assuming it's using gcc. I haven't really even checked yet. I also wonder if this is really what I had in mind. Isn't this just yet another embedded processor that happens to be running on an FPGA? It's not like these apps are getting layouts in the FPGA or something. Oh, well. I found the 288 page spec for NIOS and I'm assuming I can at least try to optimize for parallel execution or something.  Maybe I should look at an existing C to Verilog compiler that's already designed around LLVM and work with that instead.  Desicions, desicions.

[Altera_Forum]

Oh, the tutorial for this forum says it runs on nios, but you can later convert it to fpga hardware. It's right in the intro. (I just have some reading to do.)

[Altera_Forum]

The nios is basically just an embedded processor. 

Since it is made of normal fpga 'gates' it is fairly simple - so easy to model. You do get the option of writing some extra instructions - which can be useful for optimising very specific logic functions. You could even modufy the compiler to use them....  'C to Verilog/VHDL' is slightly different