boot NIOS and FPGA from EPCS flash

[Altera_Forum]

Hi all, 

 I am having problems booting up my Nios C code from EPCS. I am building my own FPGA board, not using a demo board. I'm using Quartus 15.0 and DE0 NanoBoard( Cyclone IV as FPGA) My application contains:  1. Clock Source 2. Nios II Processor 3. System ID 4. JTAG UART 5. EPCS Serial Flash Controller 6. PIO 7. SDRAM Controller  I want to use SDRAM to store instructions and data for NIOS application. In the NIOS II Processor properties reset vector is set to base address of EPCS controller. Exceptions vector is set to base address to SDRAM. In the NIOS EDS for Eclipce I can debug my application, it works. Then, want to store the FPGA configuration data and the nios firmware in the EPCS following the steps below :  1) I generate the file.hex in NIOS terminal   2) Using Convert Programming Files in Quartus, I create a JIC file using the steps below:   2-a) Select EPCS64 (that is the flash chip i'm using) 2-b) Add SOF Page -> Page 0 -> Properties -> Address mode for selected pages: Set to START and Start Address = 0x0 2-c) Add file to SOF page: Add file.sof 2-d) Properties of file.sof select Compression 2-e) Add HEX data 2-f) Add File -> file.hex 2-g) Use absolute addressing offset( the offset was given in reset vector )   3) Generate JIC file -> NO issues.  4) Program EPCS device using Active Serial Programming. Add my JIC file. Programming succesful.  5) Power cycle my board. The hardware file starts, but the NIOS never boots?   So what is going wrong? I am programming using the USB Blaster. I am also not going through JTAG.   Any ideas?  Thanks in advance   Best regards  

[Altera_Forum]

I'm only using an outdated version of Quartus so I don't know what the exact settings are now. 

On my Cyclone IV / SOPC Builder project the EPCS controller exports the serial signals out of the SOPC component and they are connected to the correct pins in my top-level file. All four of them are configured as "regular I/O" for all four of them. But again, if you get the correct information from the flash (number of blocks, block size) it means that at one point the controller did get a valid reply from the EPCS chip with an ID, so I think that this part is working.  I don't know the DE0-nano kit but do you have some example designs with the kit? If yes you can try and open them in Quartus and see how they connected them.

[Altera_Forum]

Last time I looked at the HAL code for bit-banging epcq it always does an erase before a write. 

So your writes have to cover a full flash sector.  That HAL code is a typical Altera example of making something that should be a few 100 instructions into kilobytes of code that doesn't let you do anything other than the precise action that some class/tutorial reqired.

[Altera_Forum]

Hi again, 

 Sorry for my long absence, i was on vacation. My problem is resolved now, I just changed the clock source of the EPCS CONTROLLER. The clock was driven from the system clock using a CLOCK BRIDGE. Now, the clock is driven from a PLL OUTPUT ( the system and the EPCS CONTROLLER clocks are now independent). Thank you Daixiwen & dsl for helping me.  Best regards,