component simulation in NIOS IDE

[Altera_Forum]

I'have made a design which have 2 slave ports. One of them is connected to the data master port and the second one to the instruction master port. I also have an on chip memory connecter to those ports. 

 My problem with NIOS IDE is in the configuration of the system library. When I perform simulation with all the data in the on chip ram everything is working great. But now I want to perform some simulation with my component. So I&#39;ve tryed to change the value for the automatic generation of the linker (I&#39;ve select my component instead on the on chip memory). But I get an error during compilation which is:  Creating generated.x... ERROR - Invalid .stack segment setting: top_otp_0 25 janv. 2007 13:13:45 - (GRAVE) generate: java.lang.IllegalStateException: java.lang.IllegalStateException: java.lang.IllegalStateException: java.lang.IllegalStateException: com.altera.ingenuous.GTFElement.GTFElementErrorException: <error> element in GTF script make: *** [system_description/../obj/generated.x-t] Error 1  I&#39;ve absolutely no idea of what does it mean... I&#39;ve made some research on altera website but i found nothing. If some i&#39;ve an idea of the reason of this error please let me know!  thank you all

[Altera_Forum]

A found a solution so here is the answer. 

The fact is that in the NIOS IDE system library we can only chose the name of the component and not the name of the avalon port. In my case, I&#39;ve 2 avalon port on the same component then the system library is not able to make the diffrence between a port from another .... So the solution is two create 2 wrapper for each avalon port.  DO NOT BUILD AN IP WITH 2 AVALON SLAVE YOU WILL NOT BE ABLE TO CONFIGURE THE SYSTEM LIBRARY AS YOU WANT.