Hi,
when trying to use a combinatorial custom instruction on an output to vhdl, I get needle-like impulses, which vary in width and time to each other, on an oscilloscope. This already occurs after the the .sof file is loaded into the cyc2c35 evalboard.
Because of the needles an operation under c does not make sense yet.
I used the following vhdl code in my design:
-----
--header as in tutorials
entity cust_io is
port
(
signal dataa: in std_logic_vector (31 downto 0);
signal result: out std_logic_vector (31 downto 0);
signal output: out std_logic_vector (31 downto 0)
);
end cust_io;
architecture interface of cust_io is
signal res: std_logic_vector(31 downto 0)
begin
process(dataa)
begin
res<=dataa;
result<=res;
output<=res;
end process;
end interface;
------
The sopc builder accepted the modul without any warnings.
Are the needles the result of the nios running through my vhdl code?
How can one solve this problem?
Thanks for your help in advance.
http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif
andy
