cyclone 1c20f400c7

Altera_Forum · ‎07-13-2005

Hi, I am new to altera FPGA and its NiosII. I got below problems need your great help:

1, I add some pio, uart and spi port in Full_featured example then built it without any errors.

2, In IDE, i tried to run 'hello_world' without any revise but it failed. I was noticed ''verify failed'' after bulding and running the project.

I am using quantus II 5.0 and IDE 5.0 also. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif

Altera_Forum · ‎07-18-2005

Does your reset address points to volatile memory such as DRAM?

Altera_Forum · ‎07-19-2005

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originally posted by james@Jul 18 2005, 04:45 PM

does your reset address points to volatile memory such as dram?

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Hi ,James,but what might be the pending result if I make reset address to a volatile memory?

Altera_Forum · ‎07-19-2005

the system will not work if your reset is pending