frequency the Nios II processor can support is roughtly from 20 to 120MHz

[Altera_Forum]

I changed the frequency dyanmically. The Nios II seems not to work beyond this frequency range. Does anyone know the real number?:D

[Altera_Forum]

This is a function of your device (series & speed grade) and what processor you are using. These benchmarks seem accurate for the Cyclone II and Stratix III in my experience. 

 http://www.altera.com/literature/ds/ds_nios2_perf.pdf  What device & sopc configuration are you running?

[Altera_Forum]

--- Quote Start ---  This is a function of your device (series & speed grade) and what processor you are using. These benchmarks seem accurate for the Cyclone II and Stratix III in my experience.   http://www.altera.com/literature/ds/ds_nios2_perf.pdf   What device & sopc configuration are you running?  --- Quote End ---     Thanks for you reply . I use Nios II f processor in the Cyclone III on the NEEK. :-P

[Altera_Forum]

From the reference ,it looks that the maximum frequency should be 175MHz

[Altera_Forum]

The maximum freqency will depend on other parts of the sopc system, and how full (or rather empty) the fpga is. 

The maximum will also require correct timing definitions during synthesis - since internal registers probably need to be replicated (etc).  I don't believe anything in the fpga is 'dynamic' (ie needs clocks to hold its state), so the minimum speed ought to be 0Hz - however the JTAG (and any other external interface) may enforce a minumim clock speed. Also, any external memory (SRAM) is usually run with a clock generated by PLL to be a few ns ahead of the nios clock - this won't work if you are dynamically changing the clock speed.

[Altera_Forum]

--- Quote Start ---  The maximum freqency will depend on other parts of the sopc system, and how full (or rather empty) the fpga is. The maximum will also require correct timing definitions during synthesis - since internal registers probably need to be replicated (etc).   I don't believe anything in the fpga is 'dynamic' (ie needs clocks to hold its state), so the minimum speed ought to be 0Hz - however the JTAG (and any other external interface) may enforce a minumim clock speed. Also, any external memory (SRAM) is usually run with a clock generated by PLL to be a few ns ahead of the nios clock - this won't work if you are dynamically changing the clock speed.  --- Quote End ---     Hi,thank you for your information. I used the PLL to generate several clocks and used the multiplexer to choose one of them to feed the clock of the Nios II processor at runtime. It seems that it works very well.I used bridges to gap the processor and memory(memory's clock doesn't change). I will not access any memory until the processor's clock is stable. It looks that it works very well..:confused:

[Altera_Forum]

Be very careful how you implement the clock switching. If you are dynamically switching the clock speed without putting the processor into a reset state then the pipeline and other surrounding logic may become unstable causing the processor to go into the weeds. Normally what I see others do is store off the processor state into a memory that will stay live, force the processor into reset, switch the clocks, bring the processor out of reset, the processor executes code that restores the state.

[Altera_Forum]

--- Quote Start ---  Be very careful how you implement the clock switching. If you are dynamically switching the clock speed without putting the processor into a reset state then the pipeline and other surrounding logic may become unstable causing the processor to go into the weeds. Normally what I see others do is store off the processor state into a memory that will stay live, force the processor into reset, switch the clocks, bring the processor out of reset, the processor executes code that restores the state.  --- Quote End ---       Thanks. Right now it works well. I will check whether other peripherals work in the near future