how many cycles of hardware mul/div

Altera_Forum · ‎03-19-2005

Hello!

I use QII-4.2 / NIOS2-1.1 development. There is hardware multiply and divide using LE while without DSP. I want to know how many cycles of hardware mul/div instruction with or without DSP. In data sheet, multiply use 1 cycle and divide use 3 to 65 cycles with DSP.

Altera_Forum · ‎03-20-2005

Hi,

We put some more detail on this in Chapter 17 of the Nios II Processor Reference Handbook.

See Multiply & Divide Performance on p. 17-4, and see Table 17-2 on p. 17-5.

The multiply performance depends on the FPGA target and the CPU implementation. The hardware divide performance is unaffected by the existance of DSP blocks.

Kerry

Altera