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i see the document of stratix_dev_borad, the sram .flash and Ethernet shared the address and date bus, but i donnot know why the shared address sram begin from FSE_A2,Ethernet from FSE_A1 and flash from FSE_A0?
if i make my ouw board also use shared bus ,what the principle when i assign the pin on the PCB, thank you !Link Copied
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It's based on the data width and it is in the documentation. See Table 9-1 in the Quartus II Handbook.
Cheers, - slacker- Mark as New
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i see,thank you very much!

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