how to program/download NIOS II program by using an external processor?

[Altera_Forum]

Hi, everyone. 

 I am trying to use an external processor (arm processor) to update configuration and NIOS II software program of the Cyclone III FPGA.  After some search on the altera support site, I found some solutions on how to using a externl processor to configure FPGA (JTAG+JRunner, PS/FPP configuration scheme) and how to program the FPGA configuration data into EPCS and Parallel Flash (JTAG+SFL/PFL megafunction, AS+SRunner, ...). And I also find the command line tools provided by NIOS II EDS: nios2-download and elf2flash/nios2-flash-programmer. But I doesn't find documentations on topic such as how to use an external processor to download NIOS II software program to FPGA just like command nios2-download does or how to program the NIOS II software program to EPCS or Parallel Flash just like nios2-flash-programmer does.  Does Altera provide some offical solutions for such requirement? Or does someone have done such thing before? Any help will be appreciated. Thanks in advance.  htbegin

[Altera_Forum]

You need to write an Avalon MM master that is connected external pins and use that to write to the memory. You probably have a suitable external interface already (used for other command/status info). 

The interface doesn't need to be 32bit since efficiency isn't a big problem! With an 8 bit interface I'd do something like: 4 bytes data (read/write) 4 (maybe 3) bytes address (24bit addressing is probably enough) 1 byte command status. Commands include 'read word', 'write word', 'assert reset', 'remove reset' (etc). If you don't want to assume that the Avalon cycle will be quicker than the host cycle, you'll need to read to check each cycle is complete.  Loading from a fully fixed-up elf program file is easy - look at the program headers.  Alternatively you can use objcopy to extract the sections and convert them into arm object files which can be linked as data into your arm program (you can even link the arm program with the symbol table from the nios program!).

[Altera_Forum]

Oh - you'll probably to ensure the linker script puts all the data at its required address. This might need a custom script.

[Altera_Forum]

Hi, dsl. Thanks for your reply. 

 I still have some questions about the usage of Avalon MM master and the implementation method.    --- Quote Start ---  You need to write an Avalon MM master that is connected external pins and use that to write to the memory.  --- Quote End ---    Does "the memory" include all of the following memory: FPGA Flash, FPGA EPCS, FPGA off-chip SRAM/SDRAM, and FPGA on-chip RAM?  Could I only define a private interface/protocol to communicate with an Avalon MM master? Could I use the the JTAG interface to download/programme NIOS II software program just like the nios2 command tools does? If using JTAG is possible, Could you point some related documentations out to me? Thanks.  htbegin

[Altera_Forum]

--- Quote Start ---   Does "the memory" include all of the following memory: FPGA Flash, FPGA EPCS, FPGA off-chip SRAM/SDRAM, and FPGA on-chip RAM?  --- Quote End ---  An Avalon master can write to any of the slaves (provided the conection is enabled in the SOPC builder). Writing to flash requires special protocols, but program download would normally only involve off-chip SRAM/SDRAM and on-chip RAM, and, possibly, general IO devices - all these can easily be written to.    --- Quote Start ---  Could I only define a private interface/protocol to communicate with an Avalon MM master? Could I use the the JTAG interface to download/programme NIOS II software program just like the nios2 command tools does? If using JTAG is possible, Could you point some related documentations out to me? Thanks.   --- Quote End ---  I don't think that Altera document the jtag debug interface, in any case it will need a lot more code on the host side. Remember the jtag debug module isn't an avalon master, the nios executes code from within the jtag block to access the hardware registers of the jtag interface. If you write your own avalon master, you have access to the memory (etc) independant of what the nios is doing - repeating hexdumps of memory are quite useful for working out what is going on (and without stopping the nios cpu itself).  You might actually be able to generate an 8 bit master - and have a bus width adapter generate the relevant byte enables. But some non-memory slaves may assume/require 32bit transfers.

[Altera_Forum]

Thanks again for your help. 

 I will read more documentations about Avalon interface, and figure the problem out.