interface with custom logic

[Altera_Forum]

hi ,  

my custom logic is made from hdls, schematics mixed... can these be supported by the interface with custom logic option?  thanks and regards, wayne

[Altera_Forum]

Wayne: 

 The answer is Yes (at least for the HDL--I don't know about schem., but I'm guessing no) But, I found it easier to simply create user-interfaces for each component that needed to connect to the SOPC system. Then, when your SOPC system is finished, it will have the interface signals (address, readdata, readprobe, etc.) that you connect to your logic.  In SOPC Builder: -Double click "Create New Component" -Add an interface (probably slave) -Add the signals you need

[Altera_Forum]

How about software files? any register files needed? or only write direct to the address?

[Altera_Forum]

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  my custom logic is made from hdls, schematics mixed... can these be supported by the interface with custom logic option?[/b]  --- Quote End ---    Base on my study, the component editor can&#39;t support schematics file.  <div class='quotetop'>QUOTE </div>  --- Quote Start ---  How about software files? any register files needed? or only write direct to the address?[/b]  --- Quote End ---    In component editor, you can integrate software files and register files with component IP, then in NiosII IDE, you can use them directly.  You should write register files by yourself. For example: #ifndef __ALTERA_AVALON_PIO_REGS_H__# define __ALTERA_AVALON_PIO_REGS_H__ # include <io.h> # define IOADDR_ALTERA_AVALON_PIO_DATA(base) __IO_CALC_ADDRESS_NATIVE(base, 0)# define IORD_ALTERA_AVALON_PIO_DATA(base) IORD(base, 0) # define IOWR_ALTERA_AVALON_PIO_DATA(base, data) IOWR(base, 0, data) # define IOADDR_ALTERA_AVALON_PIO_DIRECTION(base) __IO_CALC_ADDRESS_NATIVE(base, 1)# define IORD_ALTERA_AVALON_PIO_DIRECTION(base) IORD(base, 1) # define IOWR_ALTERA_AVALON_PIO_DIRECTION(base, data) IOWR(base, 1, data) # define IOADDR_ALTERA_AVALON_PIO_IRQ_MASK(base) __IO_CALC_ADDRESS_NATIVE(base, 2)# define IORD_ALTERA_AVALON_PIO_IRQ_MASK(base) IORD(base, 2) # define IOWR_ALTERA_AVALON_PIO_IRQ_MASK(base, data) IOWR(base, 2, data) # define IOADDR_ALTERA_AVALON_PIO_EDGE_CAP(base) __IO_CALC_ADDRESS_NATIVE(base, 3)# define IORD_ALTERA_AVALON_PIO_EDGE_CAP(base) IORD(base, 3) # define IOWR_ALTERA_AVALON_PIO_EDGE_CAP(base, data) IOWR(base, 3, data) # endif /* __ALTERA_AVALON_PIO_REGS_H__ */  FYI.  regards, David

[Altera_Forum]

--- Quote Start ---  originally posted by bgrattan@Dec 14 2005, 06:14 PM wayne:  the answer is yes (at least for the hdl--i don&#39;t know about schem., but i&#39;m guessing no) but, i found it easier to simply create user-interfaces for each component that needed to connect to the sopc system.  then, when your sopc system is finished, it will have the interface signals (address, readdata, readprobe, etc.) that you connect to your logic.  in sopc builder: -double click "create new component" -add an interface (probably slave) -add the signals you need <div align='right'><{post_snapback}> (index.php?act=findpost&pid=11559)  --- quote end ---    --- Quote End ---    if i understsand what u mean....which means that i just create an interface hdl...then applied in sopc builder using the custom logic option...after generating the cpu...it will appear all the exported outputs to be connected to logic outside of the cpu rite ?  currenly i&#39;m using nios I...not nios II, do i need any software driveR?

[Altera_Forum]

Wayne: 

 I don&#39;t have any experience with NIOS I. Sorry.  -Brian

[Altera_Forum]

According to my exploring experience, current SOPC builder only support packaging HDL design, so your top level design has to be in form of HDL. 

Schematic design without stand alone primitives can all be converted into HDL. Good luck!