is signed type definition synthesizable?

Altera_Forum · ‎11-22-2010

Hi all,

I'm designing a simple divider as shown below:

module divider (in1, in2, division, multiply);

//parameter

parameter DATA_WIDTH = 32;

//Input

input signed [DATA_WIDTH-1:0] in1;

input signed [DATA_WIDTH-1:0] in2;

//Output

output signed [DATA_WIDTH-1:0] division;

output signed [DATA_WIDTH-1:0] multiply;

assign division = (in1/in2);

assign multiply = in1*in2;

endmodule

I wonder is this code synthesizable since I'm utilizing the signed type definition for both input and output.

Thanks in advance,

Regards,

ty6

Altera_Forum · ‎11-30-2010

Yes it is synthesizable.

But it builds combinatorial logic (slow).

This is due to the assign, and not due to the signed types.

You should register it and pipeline it, to make it faster.

Altera_Forum · ‎11-30-2010

--- Quote Start ---

Yes it is synthesizable.

But it builds combinatorial logic (slow).

This is due to the assign, and not due to the signed types.

You should register it and pipeline it, to make it faster.

--- Quote End ---

Are you sure that the division is synthesizable?

Is this a general Verilog feature or it is a charcteristic of the synthesis tool?

Altera_Forum · ‎11-30-2010

It's a Quartus feature to infer a divider MegaFunction from Verilog and VHDL (the latter with ieee.numeric_std) code. But it's limited in part, there's no easy way to control pipelining for the inferred divider (although possible, as shown in a previous forum thread).