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hii i have progressed with the example of doing max10 rsu over uart with nios
i have the neek dev board for practicing
i have added to the qsys system of the original project that i downloaded from altera website a jtag uart for debugging
and i compiled the project and tested that works by simply printing hello world to the console in eclipse ide
the project is printing and i have added my own logic for driving leds in incrementing binary pattern to the top module and its working to , so i know for shore that hardware wise the project is working
the reset vector is pointed to the qspi flash on neek board
but now i have another problem i have changed the uart_tx and uart_rx on the top module to pmod header that is accessible on my neek dev , its a gpio header j19 so i can connect external usb_to_uart convertor to the pins on the header
because the original pin assignments in the project are going to the usb_to_uart chip on the neek board and i cant accesses this pins easily so i had to change the pin assignment
but now when i program nios_application.pof on the qspi flash and i open a terminal and restart the nios cpu by pressing the rest button i don't see any output is printed on the terminal .
i am assuming its because i changed the uart_tx and uart_rx pins on my qsys system
and my question is how do i generate the nios_application.pof after changing the serial port pins on my qsys
i have the remote_update.c file i assume that the nios_application.pof is somehow generated from the remote_update.c?
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Hello aiedb,
Have you evaluated Demonstrations/uart_usb design in MAX10_NEEK_v.1.0.7_SystemCD.zip?
After confirming the uart_usb design, we recommend to change uart_usb.qpf.
Here is a part of uart_usb.qpf file.
- #============================================================
- # GPIO
- #============================================================
- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0]
- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1]
- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2]
- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3]
- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4]
- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5]
- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6]
- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7]
- ….
- #============================================================
- # UART
- #============================================================
- set_instance_assignment -name IO_STANDARD "2.5 V" -to UART_RESET_n
- set_instance_assignment -name IO_STANDARD "2.5 V" -to UART_RX
- set_instance_assignment -name IO_STANDARD "2.5 V" -to UART_TX
- ….
- set_location_assignment PIN_Y17 -to GPIO[0]
- set_location_assignment PIN_AA17 -to GPIO[1]
- set_location_assignment PIN_V16 -to GPIO[2]
- set_location_assignment PIN_W15 -to GPIO[3]
- set_location_assignment PIN_AB16 -to GPIO[4]
- set_location_assignment PIN_AA16 -to GPIO[5]
- set_location_assignment PIN_Y16 -to GPIO[6]
- set_location_assignment PIN_W16 -to GPIO[7]
- ….
- set_location_assignment PIN_E16 -to UART_RX
- set_location_assignment PIN_E15 -to UART_TX
If you want to assign uart pins to GPIO[7:6], here is an example. Red items should be changed.
- #============================================================
- # GPIO
- #============================================================
- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0]
- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1]
- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2]
- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3]
- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4]
- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5]
- #set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6]
- #set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7]
- ….
- #============================================================
- # UART
- #============================================================
- set_instance_assignment -name IO_STANDARD "2.5 V" -to UART_RESET_n
- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX
- set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX
- ….
- set_location_assignment PIN_Y17 -to GPIO[0]
- set_location_assignment PIN_AA17 -to GPIO[1]
- set_location_assignment PIN_V16 -to GPIO[2]
- set_location_assignment PIN_W15 -to GPIO[3]
- set_location_assignment PIN_AB16 -to GPIO[4]
- set_location_assignment PIN_AA16 -to GPIO[5]
- #set_location_assignment PIN_Y16 -to GPIO[6]
- #set_location_assignment PIN_W16 -to GPIO[7]
- ….
- set_location_assignment PIN_Y16 -to UART_RX
- set_location_assignment PIN_W16 -to UART_TX
After changing the pin assignment, you need to recompile the design and generate POF again.
Regards,
Yoshiaki
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hii thanks for reply
my question is not about how to assign the uart pins
i trying to practice the max10 remote update on my neek dev board
and i saw in an741
Remote System Upgrade for MAX 10 FPGA Devices
over UART with the Nios II Processor
there is a file called nios_application.pof as a part of the files needed to do the lab
my question is about how to generate nios_application.pof file that is part of the files that is needed for Programming into external QSPI flash,
this that consists Nios II processor software application hex file only.
i have built the qsys system for the rsu design and also i have the remote_update c source file and my quistion is how do i generate nios_application.pof
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Hello aiedb,
Sorry for misunderstanding your question.
You want to run AN741 on MAX10 NEEK instead of Max10 Devkit, right?
Please me give some time to run the design on Max10 Devkit first.
Regards,
Yoshiaki
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hii you are right
i am trying to run the max10 rsu on neek , i don't have the max10 devkit i have the neek instead
i found a user guide that explains how to produce the nios_apllication.pof in the appendix i missed it i will try it out hope it will help me , if i have further questions i will get back to you .
but i noticed if i download the neek remote system update example from altera website , it doesn't come with the qsys sytem file so i can see the system in platform designer , can you send the file maybe ?
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Hello aiedb,
We can see app_image_1/OnChip.qsys, app_image_2/OnChip.qsys and Factory_image/OnChip.qsys after extracting max10_RSU.par on "Intel® MAX® 10 FPGA – Intel MAX 10 FPGA Remote System Upgrade (RSU) over UART for the Nios® II Processor Design Example". Is this the file you're looking for?
Regards,
Yoshiaki
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hii yes ' i know this file
i was wondering if there is a similar file built for rsu for the neek kit
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Hello aiedb,
You can use these files for the MAX10 NEEK KIT with no modification.
But the input clock is assumed 50MHz for OnChip.qys so that you should assign one of MAX10_CLK1/2/3_50 in NEEK to the clock.
Lastly, you need to create new pfl.sof for NEEK instead of master_image/pfl.sof for programming Nios_application.pof to QSPI memory on NEEK because pfl.sof depends on QSPI pin assignment on Max10.
Regards,
Yoshiaki
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Hello aiedb,
We have confirmed that the RSU demo design works fine on Max10 Dev Kits as below.
Let us know if you have any questions.
Regards,
Yoshiaki
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Hi @aiedb,
Greetings, just checking in to see if there is any further doubts in regards to this matter.
Hope your doubts have been clarified.
Best Wishes
BB
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hii thanks for help i have made some progress on the neek kit , i wrote my own application for update and i see that writing to the cfm is failing i will put my effort for solving this and i will get back to you , but in the meanwhile i have another question !
is the raw hex data in the rpd file gets written in the cfm ??
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Hello aiedb,
Yes, you are right.
The menu in the example software mentions below.
1: Write Image to CFM0
2: Write Image to CFM1 and CFM2
3: Trigger reconfiguration to CFM0(Factory Image)
4: Trigger reconfiguration to CFM1 and CFM 2(App Image)
Please check the software/remote_update.c in the example design for more details.
Regards,
Yoshiaki
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hii
when i press 2 to write image to CFM1 and CFM2
it asks me to enter the CFM1 start address and the CFM1 end address
in the map file that is generated by combining both(default+application) images the addresses are
0x12000 as start address
and 0xb9fff as end address
i tried to key in this addresses but i get an output that it is failing to write to addresses to cfm1!!!
note: i have my own fpga design for blinking the leds for counting pattern
and another design for to turn on the leds in sweeping pattern
i combined both of images according to the lab manual using HXD editor ,
and i also checked before by programming the designs on the kit
and i saw that they are working independently by a counting pattern and by sweeping pattern .
what is the address that i need to key in as CFM1 start address?
and what is the address that i need to key in as CFM1 end address?
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hiii
i looked at the qsys system and the addresses of the onchip flash of cfm1 is from 0x10000 to 0xb7fff so i keyed in those addresses and i get the done message in the terminal
so it seems that the writing to cfm1 with the new application is finished successfully so the programming by uart is done with out any errors
but some how after the done message i get the message request to key in the selection again and automatically the i get a message to key in start address and an end address again with ffffff although i didn't choose this option
i attached the picture to showcase what i mean
and when i press 4 to trigger the new application nothing happens the leds continue to blink with the default pattern
and even if i move the config_sel pin to 1 and turn the board off and on i don't see that the new leds pattern appears
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Hello aiedb,
Please check size of your generated file for CFM1.
In my case, factory_app1.map including Factory Image and Application 1 Image shows below.
BLOCK | START ADDRESS | END ADDRESS |
ICB | 0x00000000 | 0x00001FFF |
UFM | 0x00002000 | 0x00011FFF |
CFM0 | 0x000BA000 | 0x00161FFF |
CFM1 | 0x00012000 | 0x000B9FFF |
Start and end address of CMF 1 in the map file are 0x12000 and 0xB9FFF, respectively.
Therefor the size of CFM1 is 0xA8000 ( 0xB9FFF - 0x12000 + 1 ).
0xA8000 as decimal is 688128.
After generating pof and rpd, you can see the following files which are extracted of each block.
File | Size |
factory_app1_auto.rpd | 1449984 |
factory_app1_cfm0_auto.rpd | 688128 |
factory_app1_cfm1_auto.rpd | 688128 |
factory_app1_ufm_auto.rpd | 65536 |
The size of factory_app1_cfm1_auto.rpd should be same as 0xA8000(688128).
Regards,
Yoshiaki
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hii thanks now i have the version working for me
what i have found that i need to disable the small driver library in the bsp editor
and i need to enter the address in this form x12000 not 12000 in order for the program to work 'thanks for help a lot
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Hello aiedb,
I'm glad to hear that.
If you face another issue, please open a new thread.
Regards,
Yoshiaki
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thanks ok:)
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Hi @aiedb,
Seems that your doubts has been clarified, with no further clarification on this thread, it will be transitioned to community support for further help on doubts in this thread.
Please login to ‘ https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you for the questions and as always pleasure having you here.
Best Wishes
BB

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