niso ii simple server build issue

[sateesh999]

Hi ,

i am working with cyclone 10gx FPGA series, I was trying to create a ethernet MII interface with Nios ii eclipse .i was trying to build one simple socket ping  project in Niosii eclipse i am unable to generate .elf in any ethernet simple socket example generation getting errors as shown below .

could you please provide any one have solution resolve the issue ,if any one have faced and resolved.

Thanks

B. Sateesh

[JingyangTeh_Altera]

Hi

I believe we had a call previously arrange by your FAE regarding this issue.

This problem is due to the generated file format was changed in newer Quartus versio.

Could you try to change the line that you are facing error to the line below(line 39, tse_my_system.c) :

TSE_SYSTEM_INT_MEM_NO_SHARED_FIFO(ETH_TSE_0, 0, MSGDMA_1_TX, MSGDMA_0_RX, TSE_PHY_AUTO_ADDRESS, ADDITIONAL_PHY_CFG)

I managed to get it to compile successfully but meet an error in the elf size.

Regards

Jingyang, Teh

[sateesh999]

Hi Jing yang, Teh,

Thanks for reply for issue ,could you let us known, how we can resolve the ELF fit as of now i am newly working on this Nios II Eclipse, you have better understanding about this issue as per our discussion . Could you tell me any one solution to resolve the issue

                                              i am awaiting for your response

Thanks, Regards

Venkata Sateesh

[JingyangTeh_Altera]

Hi Venkata Sateesh

you could try increasing the on chip memory ip size to accommodate the nios application size.

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

Any update on this case?

Do you still facing any problem?

Regards

Jingyang, Teh

[sateesh999]

hi Jing yang,

     As per the your  suggestion i have increased  the onchip ram memory  but same error is coming .i have tried multiple times. Could you any way to resolve this error, 

Thanks

sateesh

[JingyangTeh_Altera]

Hi Sateesh

Could you try adding the memory to at least 500KB?

Please make sure that you are increasing the size of the onchip_memory2_0.

You will need to regenerate the project and generate the BSP again before compiling.

Regards

Jingyang, Teh

[sateesh999]

hi Jingyang,

Hi tried the given solution now able the generate the .elf ,but it not running on the hard  for ping condition, could we connect one small section to address the issue any thing do we to add modification in code as per my phy chip ADIN1200CCP32Z. to make it for simple socket ping purpose 

                                                                        i am awaiting  for your response 

Thanks 

Venkata Sateesh

[JingyangTeh_Altera]

Hi

With the TSE Soft IP, the supported phy includes the following only

National DP83848C (10/100 Mbps)

National DP83865 (10/100/1000 Mbps)

Marvell 88E1111 (10/100/1000 Mbps)

Marvell 88E1145 (Quad PHY, 10/100/1000 Mbps).

However you could add in your own PHY Definition using the API "alt_tse_phy_add_profile()"

https://www.intel.com/content/www/us/en/docs/programmable/683402/22-4-21-1-0/phy-definition.html

Regards

Jingyang, Teh

[sateesh999]

Hi Jingyang,

Thanks for your update i will check come up, if any doubt i will share you for further level.

Thanks

B.Venkata Sateesh

[JingyangTeh_Altera]

Hi Sateesh

Please note that I will be OOO the next week.

Expect some delay in replies.

Regards

Jingyang, Teh

[khtan]

Hi Sateesh,

Just checking up on this case whether you have further questions related to this case? Otherwise we would like to set this case to close pending and transition it to community support.

Thanks

Regards

Kian

[sateesh999]

Hi ,

  as per the given suggestion we are trying to update phy profile details in file as you mentioned in that file 

alt_tse_phy_profile DP83848C = {"National DP83848C", /* National DP83848C */
DP83848C_OUI, /* OUI */
DP83848C_MODEL, /* Vender Model Number */
DP83848C_REV, /* Model Revision Number */
0, /* Location of Status Register (ignored) */
0, /* Location of Speed Status (ignored) */
0, /* Location of Duplex Status (ignored) */
0, /* Location of Link Status (ignored) */
0, /* No function pointer configure National DP83848C */
&DP83848C_link_status_read /* Function pointer to read from PHY specific status register */
};how you collected these details on what base .we are also try to get above details to make one profile with our  used phy chip ADIN1200CCP32Z We could not get proper details. We are working on it .if known approach how to get those details, could guide us to move forward 

                                  i am awaiting for you response

Thanks Regards

Venkata Sateesh

[JingyangTeh_Altera]

Hi

You could find the registers for the values in the datasheet below:

https://my.mouser.com/datasheet/2/609/ADIN1200-3121141.pdf

After going through the datasheet it seems like the registers are not in the standard format below:

   * Table below show the format of the return value required by TSE driver PHY detection

   * ----------------------------------------------------------------------------------

   * | BIT | Value: Description                           |

   * ----------------------------------------------------------------------------------

   * | 31-17 | Reserved                                |

   * |  16 | 1: Error:Invalid speed read from PHY                  |

   * | 15- 4 | Reserved                                |

   * |  3 | 1: 10 Mbps link                            |

   * |  2 | 1: 100 Mbps link                            |

   * |  1 | 1: 1000 Mbps link                           |

   * |  0 | 1: Full Duplex          0: Half Duplex            |

   * ----------------------------------------------------------------------------------

You are required to create your own function to return the speed and and duplex mode.

You can see how it is for the National DP83848C PHY.

The OUI, model and rev from the ADN1200 datasheet is 0x0283, 0x2 and 0x1

[JingyangTeh_Altera]

Hi

Do you have any follow up question on this?

Regards

Jingyang, Teh

[sateesh999]

Hi,

thanks for your support to move forward,

As per your  provided input information i have made the changes as i mention below 

Step:1

i have create the structure for my phy chip in alter_avalon_tse.c as show below

alt_tse_phy_profile ADIN1200 = {"AD ADIN1200",      /* AnalogDevice ADIN1200                                  */

                       ADIN1200_OUI,          /* OUI                                                           */

   ADIN1200_MODEL,        /* Vender Model Number                                           */

   ADIN1200_REV,          /* Model Revision Number                                         */

                               0,                   /* Location of Status Register                                   */

                               0,                     /* Location of Speed Status                                      */

                               0,                     /* Location of Duplex Status                                     */

                               0,

   0,                     /* Location of Link Status                                       */

   &ADIN1200_link_status_read        /* Function pointer to configure Marvell PHY                     */

                              };                   

    /* add supported PHY to profile */                          

    alt_tse_phy_add_profile(&MV88E1111);

    alt_tse_phy_add_profile(&MV88E1145);

    alt_tse_phy_add_profile(&DP83865);

    alt_tse_phy_add_profile(&DP83848C);

    alt_tse_phy_add_profile(&PEF7071);

    alt_tse_phy_add_profile(&ADIN1200);

step2:i have created function as per datasheet details as shown below 

alt_u32 ADIN1200_link_status_read(np_tse_mac *pmac) {
alt_u32 link_status = 0;
alt_u32 reg_status = IORD(&pmac->mdio2.reg1a, 0);

/* If speed == 100 Mbps */
if(reg_status & 0x0100) {
link_status |= 0x4;
}
/* Else speed = 100 Mbps */
else {
link_status |= 0x8;
}

/* If duplex == Full */
if(reg_status & 0x0080) {
link_status |= 0x1;
}

return link_status;
}

step 3:i have add a structure for reg mapping in altera_eth_tse_regs.h as mentioned above with my phy chip

i hope i have done all modification done properly to my make my phy to work for ping application. If anything missing or anything need to correct let me known 

[JingyangTeh_Altera]

Hi

It seems okay.

Is the PHY working?

Regards

Jingyang, Teh

[sateesh999]

Hi, 

Thanks for your reply, i have shared code to testing team ,waiting for their response.

Thank, Regards

Venkata Sateesh

[JingyangTeh_Altera]

Hi

Do you have any update on from the testing team?

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh