pls help: can't read external hardware registers

Altera_Forum · ‎10-08-2006

first some descriptions of my board:

quartus: 5.1

nios2: 5.1

nios2 cpu: nios/f with data cache

uClinux: derived from nioswiki.jot.com

everthing of the uClinux seems to be ok because I have done many verifications on it and nothing is wrong.

But when I run a user application including the following codes, the uClinux automatically reboot:

#define writew(b,addr)    __builtin_sthio ((void*)addr,b)# define readw(addr)       __builtin_ldhuio ((void*)addr)
           for(i=0;i<100;i++)
{
 daq_status0=readw(STATUS2_BASE)&1; 
    fselect_counter=readw(STATUS1_BASE);
 while( daq_status0==(readw(STATUS2_BASE)&1) )
 {
                                ;
 }  
}

/*

STATUS1_BASE and STATUS2_BASE are the address of the registers in my user logic outside the nios2 cpu and are mapped to a flash-like space of the nios2 cpu.

I have verified that it's the above codes that make the uClinux system automatically reboot when I run it.

I generate the cross compiler according to "http://nioswiki.jot.com/WikiHome/OperatingSystems/BinaryToolchain" and compile my user application by such gcc command:

nios2-linux-uclibc-gcc hello.c -o hello -elf2flt

*/

then i changed my codes to the following:

#define writew(b,addr)    __builtin_sthio ((void*)addr,b)# define readw(addr)       __builtin_ldhuio ((void*)addr)
 
   for(i=0;i<100;i++)
{
 daq_status0=readw(STATUS2_BASE)&1; 
    delay(1,1);
 fselect_counter=readw(STATUS1_BASE);
 delay(1,1);
    while( daq_status0==(readw(STATUS2_BASE)&1) )
 {
  delay(1,1);
 }  
}
void delay(int loop1, int loop2)
{
  int i,j,k;
  for(i=0;i<loop1;i++)
  {
    for(j=0;j<loop2;j++)
    {
      k=j;
    }
  }
}

Then my application can function correctly in most times, but there is still a small probability to let the system reboot automatically.

My have made a lot of effort to do with the problem, but I can't still get rid of it!

can someone give me some hint or suggestion about the problem?

Altera_Forum · ‎10-09-2006

If it starts working with delays then are you sure the data being returned by your component is valid (i.e. is your status register falsely letting your software know data is ready?) Also I recommend if you haven't already done so to declare your variables volatile so that the compiler doesn't try to optimize them out on you.

If you have access to a logic analyzer then you may want to drop a PIO into your system and have Nios II write to it to capture the values Nios II is seeing (the values from status base 1 and 2). Or you could test your code below on a simple read/write PIO and validate your system that way (try eliminating all unknowns like your custom hardware first to make debugging easier).

Also do you have a watchdog in your system because if that while loop gets stuck due to the status register always returning the same value then I'd expect your system to reboot.