printf() problem after IOWR and IORD

[Altera_Forum]

Hi 

I faced to a problem with prinf() function.. in my C code when I wrote printf() after IOWR nothing was displayed out. but all the printf()s before IOWR were displayed in the jtag window. I enabled the Reduced_driver option in the BSP editor this problem was solved and I don't know how?! again with this new setting the printf() functions after IORD aren't displayed and I think the processor hanging on a deadlock! I don't have any development board and see all the results in modelsim,I mean ,can't debug my C code to see what is happening during the execution of functions. here is my C code:    # include <stdio.h># include "system.h"# include <io.h># include "sys/alt_stdio.h" int main(void) { unsigned int read=0; printf("Hello from Nios II!\n"); IOWR(TEST_LOGIC_BASE,0,0xFFFF); printf("after IOWR by reduced_driver option\n"); read=IORD(TEST_LOGIC_BASE, 0); printf("after IORD\n"); printf("value read from module: %h \n",read); return 0; }    As you see I've put printf() functions all around IOWR and IORD!!at the result just these statements are shown in jtag window:   Hello form nios II! after IOWR by reduced_driver option   I think IORD(TEST_LOGIC_BASE, 0) is executed too,because in the waves on modelsim, the read signal is asserted and the exact Data is put on read_data bus but it seems the processor(NIOS II) doesn't come back to main() to fetch the rest of the codes..! please help me if you have any experience about this problem and if you know howcan I debug my code without any develpment board and just by simulating,please aware me. thank you

[Altera_Forum]

It requires a short time from when you send the printf and when the string is actually displayed in console pane because data needs to be trasmitted out of jtag uart. I believe the printf simply sends the data to the jtag driver transmit queue. So, if your program terminates before the transmission has completed, you will not see any data. Try adding a delay loop after the last printf, before exiting the program.

[Altera_Forum]

I added this loop after last printf(): 

  for(i=0;i<9999;i++) { a=a+b; }  And think that much adding iteration was enough to assert your idea,also simulated this project for 2000us but nothing was changed. thanks for your attention cris72.

[Altera_Forum]

Just add for (; ; ); you need the infinite loop!

[Altera_Forum]

I did your suggestion dsl,but nothing happened.

[Altera_Forum]

Are you sure that your avalon slave is actually terminating the slave cycles? 

If it isn't doing that properly then the cpu will have stalled.

[Altera_Forum]

my slave custom logic is so simple because I'm just learning embeded design now.Is there any special signal that I must use in my module to tell to the cpu about termination? this module use one avalon_mm salve interface. 

  this code simply get a data from SW and put it on reg A,then put a 32bit constant data on red_data bus.  `timescale 1 us / 10 ps module new_component (avs_s0_address,avs_s0_read, avs_s0_readdata, avs_s0_write, avs_s0_writedata, avs_s0_readdatavalid,avs_s0_waitrequest, clk, reset); input avs_s0_address; input avs_s0_read; output avs_s0_readdata; input avs_s0_write; input avs_s0_writedata; output avs_s0_readdatavalid; output avs_s0_waitrequest; input clk; input reset; reg A; reg B; reg avs_s0_waitrequest; reg avs_s0_readdata; always @(posedge clk) begin if(avs_s0_write && !avs_s0_waitrequest) begin A<=avs_s0_writedata; # 1 B<=A; end end always @(posedge clk) begin if(avs_s0_read && !avs_s0_waitrequest) avs_s0_readdata <= 32'b00111111111111111111111111111111; end assign avs_s0_readdatavalid = 1'b0; initial begin avs_s0_waitrequest = 1'b1; # 10 avs_s0_waitrequest = 1'b0; # 310 $display("A = %h hex", B); end endmodule

[Altera_Forum]

--- Quote Start ---  avs_s0_waitrequest = 1'b1;  # 10 avs_s0_waitrequest = 1'b0;  --- Quote End ---    Delays implemented like this can be simulated, but not synthesized. Your code is forever holding waitrequest high. This is "OK" if waitrequest is active low, but it isn't...  Cheers,  slacker

[Altera_Forum]

slacker,I know initial block is not synthesized at all,you are right,but I just simulate my design on modelsim.I mean. I run with modelmsim in the NIOS II IDE which sends the whole SOPC design as verilog files to this program,as you can see in the code the writing part (on reg A) uses wait_request signal after# 10 and after IOWR there is a prinf() which works,but just after IORD the cpu stalls! I attched the waves reported by modelsim.

[Altera_Forum]

Your code doesn't assert the readdatavalid signal. This is now hardwired to a low level.

[Altera_Forum]

According to the avalon specification document,readdatavalid is used for piplining the transfer,and it is not used in normal transfers,anyway when I assign logic '1' to the readdatavalid or remove it completely,the whole design stops during the simulation and these erros appear in the modelsim window: 

# 245810 ns: WARNING: cpu_test_bench/M_wr_data_unfiltered is 'x'# 245820 ns: ERROR: cpu_test_bench/W_wr_data is 'x'# Break in Module cpu_test_bench at ../cpu_test_bench.v line 522    how can I use this signal? In the document of avalon, there is an example which illustrates READ and WRITE transfers without using readdatavalid signal!

[Altera_Forum]

If you don't do pipelined transfers you should remove the readdatavalid signal. 

If you don't have variable delays either, you should remove the waitrequest signal and just reply to a read request on the clock cycle following the request. In the component editor just check that the read delay is 1 (which is the default value).

[Altera_Forum]

you were right Daixiwen , I removed both readdatavalid and waitrequest signals and now the cpu continue to fetch the remaining codes and printf() functions works. thank you