"Speeding"SPI

Altera_Forum · ‎12-04-2006

Hi,

I'm developing an application based on Nios II and I'm using an SPI slave linked to

an External Master.

The code is:

#define SPI_MASK_STATO          0x01F8
void handle_SPI_interrupts(void* context, alt_u32 id)   /* Gestore SPI slave 1 */
{
  alt_u8 
         ValLetto;
         
  //volatile int* StatusSPI_ptr = (volatile int*) context;
   
  
  
    /* RICEZIONE */
    if(IsSpiRXRdy()) 
    {
      /* LEGGI DATO */
      ValLetto = spiRead(SPI_BASE);
      _BufferRxSPI = ValLetto;
            
      if(_NrxSPI < (LEN_BUFFER_SPI-2))       
      {
        _NrxSPI++; /* Overflow protection*/ 
      }
      else
      {
        /* Non incremento piu&#39; il contatore ... */
      }
    } /* Rx Ready */
   
  /* Resetto la flag */
  IOWR_ALTERA_AVALON_SPI_STATUS(SPI_BASE, 0);     
}
alt_u8 IsSpiRXRdy(void)
{
  alt_u8 RetVal;
  alt_u16 StatoRegistro;
  
  RetVal = FALSO;
  
  StatoRegistro = IORD_ALTERA_AVALON_SPI_STATUS(SPI_BASE) & SPI_MASK_STATO;
    
  if(StatoRegistro & ALTERA_AVALON_SPI_STATUS_RRDY_MSK)
  {
    RetVal = VERO;
  }   
        
 return(RetVal);
  
}
alt_u8 spiRead(alt_u32 base)
{
 /* tutti i controlli sui registri sono a carico della funzione chiamante */ 
  alt_u16 Data16;
 
  Data16 = IORD_ALTERA_AVALON_SPI_RXDATA(base);     
    
        
  return (alt_u8)Data16;
}

Master drives the NiosII Slave SPI at 1MHz.

The main problem is that the link of the speed, due to IRQ overhead in handling Rx incoming

byte, is about 1/2kHz.

If I want the link runs, master must send its byte at a very "very" slow rate ...

but it can be so slow, aren't you?

What have I miss?

Is there a way to speed up the SPI overall link ...

Thanks in advance,

M.

Altera_Forum · ‎12-06-2006

If you want high throughput you would need to resort to using a polled implementation. Using polling I think I was able to get the SPI master and slave talking to each other at 10MHz however that was the only thing Nios II was doing in my system and I remember having to put delays in.

The problem you are seeing is similar to if you have a timer that interrupts the processor at a high frequency. The processor ends up spending it's time jumping in and out of the ISR instead of performing real work.

If the external processor --> SOPC Builder protocol is not complicated then perhaps you can implement a SPI slave component that masters Avalon. That way you don't have any software impact on your throughput. Now SPI doesn't have any flow control so you have to be careful that you don't overflow the SPI slave in that case (for example if the master port can't talk to the memory it's stuffing due to arbitration).