sdram controller pll

Altera_Forum · ‎08-07-2011

Hi,

I'm trying to create a simple SOPC system with DDR memory for my NEEK (cycloneIII edition).

When I add the SDRAM controller with ALTMEMPHY the SOPC also generates the PLL with four output clocks (sysclk, auxfull, auxhalf, phy). The sysclock generated by this pll drives SDRAM controller's slave port.

Is it possible to change SDRAM controller's slave port clock?

If not, how to tune the generated pll's clocks to drive correctly the external ddr memory chip?

Thanks

Altera_Forum · ‎08-09-2011

Hi,

The problem is solved. I read wrong document before. Now I've found descsription for DDR SDRAM Controller with ALTMEMPHY.