still verify failed with on-chip memory??

[Altera_Forum]

Hi, 

I'm using SratixII 2s60 dev board kit (with two adcs and two dacs on), and I want to run "hello world" in NiosII IDE in debug/release mode. In SOPC I add components of niosIIcore/avalonMMTriBrige/CFIflashcontroller/timer/jtag_uart/onchipmemory, in niosII core I make exception address from onchipmem (offset 0x20) and reset address (offset 0x0) from cfi_flash. Also in NiosII IDE, I choose all programme/stack/heap... mems in on-chip memory, stdout/stdin/stderr in jtag_uart, system clock with timer in sopc, and timestamp timer none. In the run config, I choose jtag device "automatic(the device which has the process"(another choice is EPCS), and NiosII terminal communication device "jtag_uart".  when I run the software("hello world"), it fails with "Verify failed between xx and xx", that address is in my on_chip memory, I have read that SDRAM address verify fails quit likely, however even all run in on_chip memory(no sdram at all) still fails with verify fails, so I guess it's either the software(niosII IDE generation) or the non proper configuration in my case.  when using debug/release in NIOSII IDE and running in the jtag_uart, what is the relation of : exception address and reset address in NIOSII core configuration in SOPC, programme/stack/heap... memories, flash memory and jtag_uart, even EPCS ??? And any other advices for me ??  I've read about flash_programme user guide, but I'm afraid it's not quit clear to me, last time I used nios2 and quartus is in Y2005/06 , I find a lot changed until now. So please me and make it clearer to me?  Thanks, x.p,ma.

[Altera_Forum]

hmm, looks like, the hardware don't even get your program data... 

 have you tried to add a sys_id component to your system - recompile your Quartus Project - programm your FPGA via Quartus Programmer and then rerun the IDE Project.   If he says, that the sys_id is wrong - there may be a general problem with your programmer...

[Altera_Forum]

--- Quote Start ---  hmm, looks like, the hardware don't even get your program data...   have you tried to add a sys_id component to your system - recompile your Quartus Project - programm your FPGA via Quartus Programmer and then rerun the IDE Project.   If he says, that the sys_id is wrong - there may be a general problem with your programmer...  --- Quote End ---    Yes, I got the error, in fact from the beginning, I have searched for the answers and it seems a quit normal problem and don't have an exact explaination or solution. But I get rid of sys_id component and therefore no "sys_id not match" error information produced(of course). Then I run all the codes in on-chip-memory, still not working.  Does the programmer sitll check the sys_id "inside (just without error info)" even you do not use sys_id component in sopc??  Is this the Operation system/quartus/sopc/niosIDE software problem rather than board/hardware problem.May be I have to reinstall all the softwares...~~:confused: That's one head scratching thing for large softwares, you never kown where the problem is as it's only a black box for you... :( ---- Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Pausing target processor: not responding. Resetting and trying again: OK Reading System ID at address 0x00000000:   ID value does not match: read 0x41FFFD00; expected 0x40D7B500  Timestamp value does not match: image on board is newer than expected  Read timestamp 14:00:46 2010/01/02; expected 22:21:58 2009/12/08 The software you are downloading may not run on the system which is currently configured into the device. Please download the correct SOF or recompile. Leaving target processor paused

[Altera_Forum]

Hi  

Just verify whether the Nios II ide is taking the correct ptf file or not It should solve the problem    Just right click on the project directory and see in the System library properties there you can see the path of the ptf file taken    Might the path is wrong    regards M Kalyansrinivas