Sorry, dont know if it is proper to post a topic here.
I am working on some image pipeline on intel GPU using OpenCL.
Suppose I 3 different modules. A B C,
Input image →A→B→C→Output Image.
Currently A/B/C are processed with different kernels on gpu, and I want to do something like
breaking A/B/C into small tiles(tileA1, tileA2,...tileAn ,and tileB1...tileCn...) and make use of pipeline of them.
(because the Image size is quite big. it would take so much time if we wait unti each process is finished)
tileA1 tileB1 tileC1
tileA2 tileB2 tileC2
tileAn tileBn tileCn
I found OpenCL 2.1 has a feature named pipe, and channel(for FPGA only?)
And someone writes by using TBB we can achieve heteregenous parallel compute.
And also intel also provide openvino, I think it is using openvx? to handle the tile scheduling.
Please shed some light if you know anything about this topic.
Thank you in advance for you help and time.