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Hi ,
I am trying to run resnet 50 on FPGA using Intel opencl sdk 19.2.
Git hub : https://github.com/doonny/PipeCNN
I am getting following errors:
vinay@ign:~/Documents/opencl_fpga/PipeCNN/project$ make
aoc -v -report -march=emulator -legacy-emulator -I device/RTL -L device/RTL -l rtl_lib.aoclib -g device/conv_pipe.cl -o conv.aocx
Resolving library filenames to full paths
lib_path = device/RTL
lib_file = rtl_lib.aoclib
Resolved rtl_lib.aoclib to /home/vinay/Documents/opencl_fpga/PipeCNN/project/device/RTL/rtl_lib.aoclib
lib_path = .
All OpenCL C models were extracted from specified libraries and added to compilation
aoc: Environment checks are completed successfully.
aoc: Cached files in /var/tmp/aocl/ may be used to reduce compilation time
You are now compiling the full flow!!
aoc: Selected default target board a10gx
aoc: Running OpenCL parser....
/home/vinay/Documents/opencl_fpga/PipeCNN/project/device/conv_pipe.cl:116:16: warning: unknown attribute 'task' ignored
attribute((task))
^
/home/vinay/Documents/opencl_fpga/PipeCNN/project/device/conv_pipe.cl:259:5: error: expected a for, while, or do-while loop to follow '#pragma ivdep'
Item:for(unsigned int win_itm_xyz=0; win_itm_xyz<item_loop_bound; win_itm_xyz++){
^
/home/vinay/Documents/opencl_fpga/PipeCNN/project/device/conv_pipe.cl:259:5: error: expected a for, while, or do-while loop to follow '#pragma ivdep'
/home/vinay/Documents/opencl_fpga/PipeCNN/project/device/conv_pipe.cl:399:16: warning: unknown attribute 'task' ignored
attribute((task))
^
/home/vinay/Documents/opencl_fpga/PipeCNN/project/device/conv_pipe.cl:611:16: warning: unknown attribute 'task' ignored
attribute((task))
^
/home/vinay/Documents/opencl_fpga/PipeCNN/project/device/conv_pipe.cl:1026:16: error: 'max_work_group_size' attribute requires exactly 3 arguments
attribute((max_work_group_size(LRN_MAX_LOCAL_SIZE)))
^
3 warnings and 3 errors generated.
Error: OpenCL parser FAILED
Makefile:139: recipe for target 'conv.aocx' failed
make: *** [conv.aocx] Error 1
Any ideas on i can fix this .
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