Cherry Trail/Braswell DDR I/O port registers documentation

[B-OatPQURE]

Hi,

Documentation of the DDR I/O port registers is absent in all available documents and the MRC for the Cherry Trail/Braswell architecture is not available either.

Without the MRC I have to develop the entire memory initialisation code and without the DDR I/O port registers documentation it will be mission impossible. As Intel no longer support the MRC for the above architecture, a specification for the DDR I/O registers should be available.

I'm currently working on applying PBIOS to some products using the Atom Z8350 architecture, so I have an urgent need of the documentation. Since Intel made the MRC unavailable, it's unfortunate that they left out the documentation of these crucial part. The architecture is not EOL and still used in may products, so it's reasonable to have some support for it.

Best regards,

B-O Bergman

PQURE Technology

[DeividA_Intel]

Hello B-OatPQURE,  

Thank you for posting on the Intel® communities. I am sorry to know that you cannot find the documentation needed. 

In order to better assist you, please provide the following: 

1. Are you using the Intel Atom® x5-Z8350 Processor?

2. Are you working for a company? If so, what is the name of the company

3. Can you provide me with more information about the project that you are working on?

4. What does "MRC" stand for?

Regards,  

Deivid A. 

Intel Customer Support Technician 

[B-OatPQURE]

Hi,

Answers to the question follows:

1. Are you using the Intel Atom® x5-Z8350 Processor?

Yes, I'm using it on a Rock Pi X, UP Core and UP Board.

2. Are you working for a company? If so, what is the name of the company

Yes, I'm working for PQURE Technology.

3. Can you provide me with more information about the project that you are working on?

I'm adopting our BIOS (PBIOS) to the above boards. You can visit www.pqure.com for more information about PBIOS and our company.

4. What does "MRC" stand for?

MRC stands for Memory Reference Code. Intel normally provides MRC for integration in UEFI BIOS or adoption for legacy BIOS and boot loaders. They stopped support for Z8350 and thus MRC is no longer available.

I have Intel SNDA and had access to MRC for previous architectures. PBIOS is used in several products where quick boot is essential. It has been applied to some Kontron boards, all Minnowboards and some Mini PCs with the Baytrail architecture. I'm now working on applying it to the following Z8350 boards: Rock Pi X, Up Core, Up Board and Latte Panda.

Best regards,

B-O Bergman

[DeividA_Intel]

Hello B-OatPQURE, 

Thank you for the information provided 

I will proceed to check the issue internally and post back soon with more details. 

Best regards, 

Deivid A.  

Intel Customer Support Technician 

[B-OatPQURE]

Thanks,

Looking forward to your reply!

[DeividA_Intel]

Hello B-OatPQURE, 

Based on your request and the research performed, I recommend you to Intel® Resource and Documentation Center (RDC) and look for the Memory-mapped Input/Output (MMIO) Cherry Trail document.

Create an account: https://www.intel.com/content/www/us/en/support/articles/000058073/programs/resource-and-documentation-center.html

If that is not what you need, try to check with the Intel® Resource and Documentation Center (RDC) team as all of that information is confidential.

Please keep in mind that this thread will no longer be monitored by Intel.  

Regards,  

Deivid A.  

Intel Customer Support Technician  

[B-OatPQURE]

The documentation "Memory-mapped Input/Output (MMIO) Cherry Trail" refers to the graphics controller which is one part of a several chapter long description.

I have checked out the documentation I have from Quark, Cedarview, Baytrail, Braswell and Cherry trail. Only Cedarview has a description on the DDR I/O (MIO) unit, but only by name and not register details. Quark MRC is available as open source, but limited to 800 - 1066 MHz, single channel and 32-bit memory bus. I have the MRC for both Cedarview and Baytrail architectures, but they are limited to 800 - 1066 MHz and 800 - 1333 MHz respectively.

For both the Cedarview and Baytrail architectures modified the code to work with PBIOS. For Cedarview I also developed my own MRC in assembly language, compliant with the MRC in C language.

The problem is that Intel will not give me access to the MRC for Z8350 as they don't want to support it. The Z8350 is not EOL, so it makes no sense to don't provide me with the MRC or documentation of the MIO (DDR I/O) unit.

For the record, I have never been a burden for Intel support regarding adoption of MRCs to our BIOS. Intel don't have to support us in any other way than providing the documentation that the law entitles us to. In the current situation, we as the only BIOS vendor in EU are prohibited from applying our BIOS to Intel silicon which is a violation of the competition law.

The European Commission Competition DG, took up a case when I was not allowed premier support. This was sorted out. Now I have premier support, but I'm not offered any support so the result is the same. It would be great if could focus on my work, get the documentation I need and be spared from the effort of consulting EU. If Intel continues the silence treatment in premier support, I will have no choice but reopen the case.

I want no trouble. I want to have the same opportunity as the competitors, that's all. It would be fair as we have a SNDA that normally covers reference code and other documentation. MRCs and other reference codes has been sent to me in the past, so why can't I get anything now?

Best regards,

B-O Bergman

PQURE Technology