Intel core SPI0 for TPM

[yzjunnn]

hi,

I've recently been learning about the SPI protocol for CPU to communicate with tpm.

However, I found that the requirements for SPI timing in the Intel core utral process datasheet are inconsistent with the TPM specification requirements.

The TPM specification requires the use of SPI mode0, where the master-slave drives the data on the falling edge of the clock and samples the data on the rising edge.

But the Intel chip datasheet timing requirements seem to require the falling edge of the clock to be sampled. This seems to be contrary to spi mode 0

Can someone help me with this question？

[FrancisP_Intel]

Hello yzjunnn,

Thank you for posting in Intel Communities. We see that you are reporting a discrepancy between the TPM specification and the processor's datasheet. We'll see what we can do to assist you with this. For us to better understand this report. Could you share the links or references to the articles and documents highlighting the inconsistencies between the Intel core ultra processor datasheet and the TPM specification requirements? Also, may we have the specific model of the processor in question?

This information will greatly aid us in understanding and addressing the issue more effectively. We will be waiting for your response.

Best regards,

Francis Ryan P.

Intel Customer Support Technician

[yzjunnn]

hi,

Thanks for the reply. 

This is the TPM protocol specification that I learned. Section 7.4.6 of the specification describes the transmission requirements for TPM SPI. It requires the master and slave to use rising edge sampling

https://trustedcomputinggroup.org/wp-content/uploads/PC-Client-Specific-Platform-TPM-Profile-for-TPM-2p0-v1p05p_r14_pub.pdf

But in section 13.0 of this specification, the electrical specification describes the timing of SPI0, and the requirement appears to be falling edge sampling.

https://www.intel.com/content/www/us/en/content-details/792044/intel-core-ultra-processor-datasheet-volume-1-of-2.html

I don't know if my understanding is correct, please help answer this question.

Thanks

[FrancisP_Intel]

Hello yzjunnn,

Thank you for sharing the requested information. Please give us some time to check our resources. Greatly appreciate your help.

Best regards,

Francis Ryan P.

Intel Customer Support Technician

[NormanS_Intel]

Hello yzjunnn,

We sincerely appreciate your patience. It is with gratitude that we acknowledge the feedback you have shared with us. Rest assured, we are in the process of updating the information accordingly. In the meantime, we kindly ask you to follow the TCG specifications.

Should you have any further inquiries or require additional support, please do not hesitate to reach out. We are here to assist you and will await your correspondence.

Best regards,

Norman S.

Intel Customer Support Engineer

[NormanS_Intel]

Hello yzjunnn,

I wanted to check if you had the chance to review the information I posted. Please let me know at your earliest convenience so that we can determine the best course of action to resolve this matter. 

Best regards,

Norman S.

Intel Customer Support Engineer

[yzjunnn]

Hello,

Thanks for the answer. 

That means I should be guided by the TCG specification. The SPI master and slave use rising edge sampling？

Does the Intel specification define sample timing with half-cycle delayed samples, which would seem to explain it？

Thanks