PCIe 4.0 lane margin tool

[Aimee1]

It always show "ClearErrorLog" when I run Intel lane margin tool, log please refer to below:Error Count Limit : 5
Starting Time Margining at Right
Link succesful trained to L0!!!
Link successful trained at Gen4!!!
Time Margin Right Step = 0 : Errors = 0 : UI = 0.000 % : UI_Time = 0.000 ps
Time Margin Right Step = 1 : Errors = 0 : UI = 6.250 % : UI_Time = 3.906 ps
Time Margin Right Step = 2 : Errors = 0 : UI = 12.500 % : UI_Time = 7.812 ps
10ms has passed since 'ClrErrLog' command was issued. Exiting Margining
Time Margining Right: ('NA', 'ClearErrorLog command failed', 0, 0)

I don't known the reason that cause  'ClrErrLog' , can you give me some information?

Thanks!

[AndrewG_Intel]

Hello @Aimee1

Thank you for posting on the Intel® communities.

For information and support regarding the PCI Express* (PCIe*) Lane Margin Tool for PCIe 4.0/5.0, please refer to the Intel® Developer Zone. To access the Support Resources, please register and create an account.

Support options can be found under this link: Get Help. The Developer Zone is the proper channel of support for this type of request.

We will proceed to close this thread now. Thank you for your understanding.

Best regards,

Andrew G.

Intel Customer Support Technician

[zuiding_666]

Hi Aimee,

Has this problem you met been resolved? That's why? I also meet the same problem.