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10 Base ethernet Transmitter issues

Altera_Forum
Honored Contributor II
‎04-15-2010 06:03 PM
1,491 Views

Hey, 

 

I know that is not the most proper area to place this question but i think there are many who can give me a tip on this matter. 

 

When i have to design the circuit , i have to implement anything more than a RJ45 Filtered Jack (with transformers) ?  

Like this : http://uk.farnell.com/amphenol/rjmg163118101nr/jack-10-100-base-t-rohs5/dp/1357436 

http://uk.farnell.com/productimages/farnell/standard/135743307-40.jpg  

 

Ps. The ethernet packets (UDP) will pass through hub.  

I am really curious if i will face any collisions. 

 

 

 

Thank you for your interest.
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Altera_Forum
Honored Contributor II
‎04-15-2010 10:15 PM
765 Views

The driver electrical specification and requirements of collision avoidance in half-duplex operation of 10BASE-T twisted-pair ethernet medium can be found in IEEE Std. 802-3, Section One, Clause 14. 

 

In a short, the interface has to listen on the receiving channel for colliding packets during transmission. 

 

The standard can be downloaded for free within the Get IEEE 802 program: http://standards.ieee.org/getieee802/portfolio.html
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Altera_Forum
Honored Contributor II
‎04-22-2010 11:32 AM
765 Views

Thanks for the reference FVM, i got some vital specifications about my needs. 

 

But i have a question, i had been concitrated on the fpga4fun.com 10base ethernet project (http://www.fpga4fun.com/10base-t0.html) and i am asking: It will be any clock issue if I use this project (20Mhz) combined with a Phy Chip (25Mhz) ?  

 

I am cornered on this matter and i dont know what to decide. 

 

1.Follow the fpga4fun project without PHY and face collisions, or 

2.Modify the source code and add a PHY chip to solve these problems. 

 

Ref: http://www.fpga4fun.com/10base-t0.html (http://www.fpga4fun.com/10base-t0.html) 

 

PS. I will only implement the Transmittion part ( Half Duplex) 

 

 

Thank you for your time. :) 

Friendly Giannis
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