10 errors on my analog input signal (smart led) code pls help!

[Altera_Forum]

library IEEE; 

use IEEE.STD_LOGIC_1164.all; ENTITY sirisha IS port ( temp :in std_logic_vector(6 downto 0); CLK :in std_logic; enable :in std_logic; day , night :out std_logic; disp :out std_logic_vector(2 downto 0) ); end sirisha;  ARCHITECTURE structure of sirisha IS signal temp :std_logic_vector(6 downto 0); signal CLK :std_logic; signal enable :std_logic; signal day,night :std_logic; signal disp :std_logic_vector(2 downto 0);  constant TCLKH_C :time:=5ns; constant TCLKL_C :time:=TCLKH_C; constant TCLKL_C :time:=(TCLKH_C + TCLKL_C); constant TRDELAY_C :time:=TCLKL_C; constant TRHOLD_C :time:=1ns;  component sirisha port ( temp :in std_logic_vector(6 downto 0); CLK :in std_logic; enable :in std_logic; day , night :out std_logic;  disp :out std_logic_vector(2 downto 0) ); end component;  cur_st_process (CLK,enable) begin if (enable='0') then cur_st <= start; else if (CLK'event and CLK='1') then  cur_st<=next_st; end if; end process cur_st_pr;  nxt_st_process (cur_st,temp) --next state comb. circuit begin if(temp>"1000110")then nxt_st<= day; else if (temp<"0110010") then nxt_st<=night; else nxt_st<=cur_st; end if; end process nxt_st_pr;  reg_pr : process (enable,CLK) begin if (enable='0') then day <='0'; night <='0'; disp <="000";  else day <='1'; night <='1'; disp< ="001"; end if; end process reg_pr;  begin (temp=>temp,CLK=>CLK,enable=>enable,day=>day,night=>night,disp=>disp); end structure;     i want the code to turn the led on(high) or low(off) based on the value of nxt_st_process (cur_st,temp).i.e at x>70 ADC value the leds should on else te leds should go off when it is at 50 adc value...i cant make it to compile successfully..pls help

[Altera_Forum]

You have a lot of issues I am not good in VHDL but you need a begin after your architecture and before your concurrent statements also for else if it should be elsif. In your process blocks you name the process but you need a colon and word process before your brackets. Here is some info. 

 http://www.gmvhdl.com/process.htm  http://www.vhdl.renerta.com/mobile/source/vhd00005.htm  http://www.ics.uci.edu/~jmoorkan/vhdlref/ifs.html