10170 Verilog Error

[Altera_Forum]

module tcounter (CLK, CLR, ENP, ENT, Q); 

input CLK;  input CLR;  input ENP;  input ENT;  output [3:0] Q;  wire [3:0] inc;    treg4bit register(  .CLK(CLK),  .IN(inc),  .RESET(~CLR),  .OUT(Q)  );  if (ENP & ENT) begin  if (Q[2] & Q[1] & Q[0]) begin  inc <= 4'b1111;  end  else if (Q[1] & Q[0]) begin  inc <= 4'b0111;  end  else if (Q[0]) begin  inc <= 4'b0011;  end  else begin  inc <= 4'b0001;  end  end endmodule  Errors: Line 15 (10170): near text if, expecting endmodule Line 19 (10170): near text "&", expecting "." or another identifier Line 22 (10170): near text ")", expecting "." or another identifier   Any help would be much appreciated http://www.alteraforum.com/forum//images/icons/icon11.png

[Altera_Forum]

Hi mage76, 

 there are several issues in your example: As inc is a wire, you need an assign statement for logic. Or define inc as reg, then you could use always @*. 'inc' (as reg) is not initialized, this will infer latches, i am sure you don't want this! Or use inc as reg in combination with 'always @(posedge CLK)', this will infer FFs instead of pure combinatorial logic.  If your intention is to create combinatorial logic only you should use '=' instead of '<='.

[Altera_Forum]

I say this in the nicest possible way - you need to find a good book or tutorial on how to write Verilog code. this (http://www.asic-world.com/verilog/verilog_one_day.html) is a good starting point.