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10CL120ZF484I8G Default state

monisha
Beginner
214 Views

Hi,

 

Please let me know the default state of all GPIO of  10CL120ZF484I8G after power up(before programming)?

We are going to evaluate the all peripherals of the board without programming the FPGA. We are planning to tap the wires and connect to external analyzer for validate the circuit. Will this cause any problem to FPGA? Kindly reply.

 

Thanks,

Monisha OM

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3 Replies
monisha
Beginner
187 Views

kindly reply

AminT_Intel
Employee
171 Views

Hello,

 

Please refer to page 146 & 147 for detailed explanation on this question from this document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51003.p...

 

Thank you/

AminT_Intel
Employee
70 Views

 We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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