10CL120ZF484I8G Default state

[monisha]

Hi,

Please let me know the default state of all GPIO of  10CL120ZF484I8G after power up(before programming)?

We are going to evaluate the all peripherals of the board without programming the FPGA. We are planning to tap the wires and connect to external analyzer for validate the circuit. Will this cause any problem to FPGA? Kindly reply.

Thanks,

Monisha OM

[monisha]

kindly reply

[AminT_Intel]

Hello,

Please refer to page 146 & 147 for detailed explanation on this question from this document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51003.pdf

Thank you/

[AminT_Intel]

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