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Altera_Forum
Honored Contributor I
861 Views

10M50DA clock frequency PLL in EPE

Hi ALTERA-forum, 

 

I am new to the FPGA design and now want to start with the EPE. Now I have two problems. One with the frequencies and another with the dissipation. 

 

 

1. I want to use the 10M16DA F484 because of the DDR3 interface support. 

Now I want to calculate the estimated power dissipation. Probably later I will switch to a higher FPGA like the 10M50DA F484. To calculate the worst case power dissipation, I decided to use the EPE and the 10M50DA model. 

At this point it is not known what the FPGA will do in the future so no design is ready at this point. 

So using the Quartus for all the data is no solution. 

Nevertheless I am a bit confused with the EPE and the maximum Clock and PLL frequency. 

So I looked up alot datasheets when I was reading the handbook/guide for the EPE.  

I stopped when I was looking for the max frequencies. For the PLL it is given in the sheet for the clock and PLL. It is 1300MHz like the EPE said. 

But for the clock the maximum frequency is not given in the sheets. Only the EPE is given out a warning that the max frequency is 600MHz. So how is the frequency calculated or where can I find this hint/data in the datasheets? I looked up every sheet which is recommended to the EPE or the datasheet of the MAX10 but I cant find this value.  

Please can anyone help me? 

 

2. I called the ALTERA support and get the EPE filled up with some data which are a bit irreal (the support said it). But its ok because I wanted it so for the worst case. For example it is really unrealistic that all LEs are toggling at the same time. 

So I looked up his data and filled in my own. At the end my electrical Power was round about 7W.  

Is this possible? I know that there are 30% margin for the load current, but I dont know if 7W are to less. I calculated the power using LVCMOS at 3.3V, because I know that at least 140 pins are use as bidirectional LVCMOS signals. 

So what is the most realistic electrical power the 10M50DA can consume? Are there any data or experiences in this point? 

 

 

Best wishes and thank you for the help. 

 

 

PS: Sorry if my English isnt that good. If there any questions in understanding my "Wirrwarr" please ask and I will try to do my best again.:)
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4 Replies
Altera_Forum
Honored Contributor I
35 Views

See Table 27 in the MAX 10 datasheet for the PLL specs: 

 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/max-10/m10_datasheet.p... 

 

According to this data sheet the max VCO frequency is 1300MHz and the max output clock frequency is 472.5MHz for the fastest speed grade. However, Table 26 for the clock tree specs says the max clock frequency is 450MHz. So that's realistically your limit. There are lower frequency limits for things like embedded multipliers and block RAMs. All of the information is in the data sheet. 

 

I can't speak to the max power a MAX 10 device can use. If you're trying to estimate currents so you can pick power supplies a good reference point would be to look at the schematic and BOM for MAX 10 development kits and see what regulators were used on those. If you're concerned about heat removal for thermal management then you'll have to try to come up with a more realistic worst case for your design rather than just maxing out everything in the EPE spreadsheet. 

 

The MAX 10 dev kit from Altera uses the 10M50D, so that should be a good reference point: 

 

https://www.altera.com/products/boards_and_kits/dev-kits/altera/max-10-fpga-development-kit.html 

 

You can download the schematic and BOM from this page. 

 

By the way, your English is excellent! 

 

Bob
Altera_Forum
Honored Contributor I
35 Views

Hi Bob, 

 

thank you for the reply. 

I found this information too, but was a bit unsure about the Clock max frequency, because, as you said the datasheet shows a maximum frequency of 472.5MHz but the spreadsheet shows 600MHz. 

 

In case of the max power for the MAX10 device I don't just maxing out the parameters. I looking up for the signals the FPGA will working with and their voltage level and operating frequencies. Then I put a little margin on the frequency. 

 

The data to the Dev Kit is looking interesting.  

The Power tree looks quite similar to mine. Instead of the 12V to 5V I am using 24V to 3.3V. I dont want to use FTDI or HDMI, so I think I am fine by using the 3.3V directly converted from teh 12V. I just have to look for the current ranking. 3.3V @ 3A will do fine. There are just VCCIO and SPI on this rail. 

Thank your for the links. They help me alot. 

 

 

Best Regards 

Jérôme
Altera_Forum
Honored Contributor I
35 Views

Hi Bob, 

 

thank you for your reply. 

I checked the links and have to say thank you. The first one i knew but I must have missed the second one. 

The data for the power rails are quite common with my calculated data. I will only use LVCMOS signals and probably DDR3 Flash so my expected current for some rails wont be this much. 

 

Thank you very much! 

 

Best regards. 

Jérôme
Altera_Forum
Honored Contributor I
35 Views

Glad it helped, Jérôme. Good luck with your project! 

 

Bob
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