16-bit 4 inputs interfacing with 16-bit 1 input of DCFIFO

[Altera_Forum]

hi,  

 i'm thinking to interface these 16-bit 4 inputs to 16-bit 1 input of DCFIFO. i want the data to be written in sequence, starting from Q1 to Q4. when wrreq is asserted in DCFIFO, the output data from packetconverter is written into FIFO in sequence manner[Q1-->Q2-->Q3-->q4] and expected to be finished after 4 clock cylces(1 cycle for each data). any idea how to do that?  FBD is attached.   Thanks

[Altera_Forum]

i suggest to add an intermediate module between the two blocks, see the picture in attachment, you must feed that block with two clock signals : the fifoclock input determines the writing speed to the fifo, and the fulldataclock input is the clock that synchronizes data on Q1, Q2, Q3 and Q4. I assumed that on the rising edge of fulldataclock, data on Q1,...,Q4 changes. In order to do the task correctly, the frequency of fifoclock must be at least 4 times bigger than the frequency of fulldataclock. 

 the material description of the block is in the file inter4to1.v in attachment   note : i didn't test the verilog code yet, but logically it must work

[Altera_Forum]

the verilog file that i have sent to you contains both the 4to1 mux so as the control unit, even if it's not explicit. i've done a simulation test to the file inter4to1.v and the logic is working as expected, see a screen shot of the modelsim simulation in attachment ...

[Altera_Forum]

ok. need to study this code. normally, i create separate code for datapath and control unit. 

 by the way, why should i need two different clocks? fulldataclk and fifoclk? can i just use the same clock?  thanks

[Altera_Forum]

first, does the clk input in the packetbitconverter block synchronizes the Q1...Q4 outputs ? (does the Q1...Q4 outputs changes on each edge of clk ?)if yes, then fulldataclk could be connected to clk 

fifoclk is the clock connected to the wrclk of the fifo, choose for its frequency, any value that's at least 4 times bigger than fulldataclk (so as to be able to stock all the four values Q1..Q4 in the fifo, before they change)

[Altera_Forum]

--- Quote Start ---  first, does the clk input in the packetbitconverter block synchronizes the Q1...Q4 outputs ? (does the Q1...Q4 outputs changes on each edge of clk ?)if yes, then fulldataclk could be connected to clk.  --- Quote End ---    yes, the output will be available at posedge of the clk.     --- Quote Start ---   fifoclk is the clock connected to the wrclk of the fifo, choose for its frequency, any value that's at least 4 times bigger than fulldataclk (so as to be able to stock all the four values Q1..Q4 in the fifo, before they change)  --- Quote End ---    right now, i used the same clock as clk for fifoclk(wrclk). the output at Q1 to Q4 will not change until Q4 has been transferred to fifo. is that possible to do so? i will need to de-assert "en" signal to clear the Q outputs.   thanks