1GHz Counter

[Altera_Forum]

I would like to make a multichannel scaler device using an FPGA. It continuously counts a 1GHz clock and latches at an external event trigger, then increment the number in a memory which is addressed by the latched counter value. The external event rate is low, say 1 kHz, but I need at least a 2 ns resolution with the timing of the random event. 

Is it possible to count (23bit) a 1GHz clock in an appropriate FPGA chip? What is the recommended device? Sincerely.

[Altera_Forum]

A 1 GHz clock is not possible. The maximum supported by the clock tree is 800 MHz for a Stratix IV. 

 Maybe you can get the job done by using a 500 MHz clock and DDIO to sample the input signal at both edges of the clock?  You probably won't be able to run the 23 bit counter at 500 MHz either. Since your event rate is only 1 kHz, there may be some way to work around this.

[Altera_Forum]

Such speed is only available at serdes(lvds). You might try pass the event as serial line onto an lvds. then read the parallel word. 

You will need adequate data transition for serdes clock recovery hence one suggestion is pass a stream of regular ones/zeros and the event gets embedded as a string of continuous ones. When you read the parallel word you will count the "all ones" word length.Not a classical idea but might worth considering it.

[Altera_Forum]

Then again, this really looks like a job for a TDC. 

 Ie, http://www.acam-usa.com/gp2.html

[Altera_Forum]

Thank you very much for your prompt replies. 

I understand that such a high frequency is not covered yet by a general purpose FPGA. 1) I take a look at TDC-GPX from ACAM and the device seems to be fine. 2) the serdes idea is very interesting. I will take a look at the possibility. I am wondering whether the transceiver function of FPGA (Cyclone IV has 3.125 Gbps transceivers) can be used for such a purpose.