Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20704 Discussions

2 Transceivers PLL issue

gbessa
Novice
556 Views

Hello,

 

I'm using Cyclone 10 GX Development Kit. I'm trying to use the 2 SFP ports at the same time. I already used one and everything was good: I used Triple Speed Ethernet IP (PCS+PMA version) + ATX PLL + Reset Controller.


Now, for the 2 SFPS, I added to my Platform Designer another instance of each IP with exactly the same parameters, but there's a Critical Warning about PLL Spacing:

"Critical Warning(18234): ATX PLLs are 0 ATX PLLs apart. For ATX PLL VCO frequencies between 7.2 GHz and 11.4 GHz, when two ATX PLLs operate at the same VCO frequency (within 100 MHz), they must be placed 6 ATX PLLs apart."

 

So my questions are:

1) How to solve/arrange PLL Spacing?
2) Can I use the same PLL for both transceivers?
3) If yes, how should I connect the signals? should I use the same Reset Controller for both transceivers?

 

0 Kudos
1 Solution
ZiYing_Intel
Employee
456 Views

Hi,


1) How to solve/arrange PLL Spacing?

ATX PLLs' VCO frequency offset must be 100 MHz apart. For further information about the PLL Spacing, you may refer to link below Section 3.1.1, https://www.intel.com/content/www/us/en/docs/programmable/683054/20-1/transmit-plls-spacing-guidelines-when.html

 

2) Can I use the same PLL for both transceivers?

It need depends on the transceiver type that you use. If you are using the XCVR, you can do the PLL sharing.

 

3) If yes, how should I connect the signals? should I use the same Reset Controller for both transceivers?

You need to aware some rules when you are doing the PLL sharing. You need to ensure that you are using the same frequency, same refclk and same side of bank.

You can use the same Reset Controller for both transceivers if you want to control the resets at the same time.


Best regards,

Zi Ying


View solution in original post

0 Kudos
3 Replies
ZiYing_Intel
Employee
470 Views

Hi,


Thanks for submitting the issue.

Please do allow me have some time to look into the issue and I will get back to you with findings.


Best regards,

Zi Ying


0 Kudos
ZiYing_Intel
Employee
457 Views

Hi,


1) How to solve/arrange PLL Spacing?

ATX PLLs' VCO frequency offset must be 100 MHz apart. For further information about the PLL Spacing, you may refer to link below Section 3.1.1, https://www.intel.com/content/www/us/en/docs/programmable/683054/20-1/transmit-plls-spacing-guidelines-when.html

 

2) Can I use the same PLL for both transceivers?

It need depends on the transceiver type that you use. If you are using the XCVR, you can do the PLL sharing.

 

3) If yes, how should I connect the signals? should I use the same Reset Controller for both transceivers?

You need to aware some rules when you are doing the PLL sharing. You need to ensure that you are using the same frequency, same refclk and same side of bank.

You can use the same Reset Controller for both transceivers if you want to control the resets at the same time.


Best regards,

Zi Ying


0 Kudos
ZiYing_Intel
Employee
420 Views

Hi,


Since no hear any feedback from you, I am now close the issue. If you have any question after the case closed. Please do feel free to submit another issue.


Best regards,

Zi Ying


0 Kudos
Reply