2 clock domains or NOT?

Altera_Forum · ‎01-22-2010

Hello,

Just need a suggestion from experiensed engineers how the following situation can be considered.

I have a PLL which generates 20 Mhz from 24Mhz. Next I feed it outside an FPGA. Next I take this 20Mhz output as a clock input for a second PLL to generate the 25Mhz clock. All my project (all logic and registers, except first PLL of course) works on this 25Mhz clock.

Should we consider this hypothetical design as a 2 clock domains design? What problems can be connected with such an architecture?

Any suggestions are welcomed.

Please do not ask why i just don't generate 25 from 24 using one PLL or why i don't cascade PLLs via clock network.

This is to discuss PLLs/FPGAs features.

Thank you.

Altera_Forum · ‎01-22-2010

The 20Mhz and 25MHz clock domains should be treated as two separate clock domains. However, in this particular case there is a relationship between the two.

Problems? Problems between clock domains normally only occur when you are trying to pass logic between the two domains. (A deeper discussion might get into physical problems with multiple domains (routing resources, jitter, noise, etc.). If you are not crossing clock domains, then there is no issue. If you are crossing domains then you need to use proper domain crossing techniques (dual-clock FIFO(s), RAM, synchronization circuits, etc.).

Jake