3 Boundary Scan Cells Operating Incorrectly

[Altera_Forum]

Who can solve this Cyclone III problem? 

 Three boundary scan cells on my board in my CycIII EP3C40F780 behave as if they have 500 Ohm resistors inbetween the driver and the pin. (Used as SSTL2 for DDR after config and work just peachy).   - I have the latest BSDL (1.01) from the Altera BSDL website - I'm holding the FPGA out of configuration - The test is working 99% for this 2-FPGA, 3 DDR, 3 Flash, etc design already with the exception of only these 3 pins.   These pins are AC11, AH18, and AF18 on the FPGA, and they have no other special function or dedicated function according to data sheet.   Each of the pins happen to be connected from the FPGA to DDR IC I/O. Two of the 3 problem pins are WE_N and D7 to one DDR IC. The third problem pin is BA1 to a different DDR IC.   When driven HIGH by the test software, the voltage only gets up to 1.38V. When driven LOW by the test software, the voltage only drops to 1.14V. For all other I/O connected to DDR, the voltages are 1.95V and 0.57V, respectively.   These voltages are consistent during testing ... whether I run the test at-speed, or whether I step through it, test vector by test vector. So it doesn't seem to be a capacitance or inductance issue.   It happens on all 20 of 20 boards, and PCB layout and Netlist is A-OK.   Most compelling ... the incorrect voltages are measured to be the same, whether right on the BGA, on a via, on the termination resistor, or at the memory pin. So even right at the driver source on the BGA, the voltage is wrong.   When I remove the 51 termination resistors, the voltage then goes to the correct 0V to 2.5V levels, as the banks are defined.   There is a termination resistance of 51 Ohms from the DDR line to a termination voltage ... 1.25V. So, a 500 Ohm resistance internal to FPGA would give me roughly the 1.38V and 1.14V I'm seeing.     All this together adds up to = the Altera device seems to not be able to drive these 3 pins to the correct levels, as if there is a drive-strength problem, or series resistance of about 500 ohms between the driver and BGA.   It seems far fetched, but it seems like an Altera CycIII design issue with the boundary scan cells. The BSDL file has these 3 I/O pins defined as all other general I/O, so its hard to see it as a BSDL file issue.   Thoughts anyone?

[Altera_Forum]

No thoughts anyone? 

 Three boundary scan cells behave in a drive-strength limited fashion, or incorrect output voltage level fashion.   If you were sure the BSDL file was correct, that the FPGA is definitely not configured at the time of test, and the board layout and physical build is proven, what else would you look at?   I have Altera support looking into it, as well as Corelis (developer of boundary scan test software and hardware).

[Altera_Forum]

An answer!!! (I'm not crazy ... it is a Cyclone III (EP3C40) design error :eek: ). 

 Altera Support has confirmed, through their own independant testing, that these 3 pins on ALL EP3C40 devices have a current limit issue when running a boundary scan test on an unconfigured device!   do not use af18, ah18, or ac11 on the ep3c40. Just don't use them. If you are going into a high enough impedance, they'll actually work just fine, but to be safe, I'd just leave them as No-Connects on your design.   Again, if you use these three pins, you will have a current limit issue in boundary scan testing of unconfigured devices. So that means DO NOT use these pins with DDR termination (~50 ohms), or other fairly low resistance applications. And according to my testing, I would actually not go lower than 1 kOhm.   If its too late for you, the work around is to create a boundary scan test for post-configuration. In order to get the same amount of coverage though, you will have to create a test image that has all pins (that aren't reserved) as bi-directional I/O. Then you'll have to create a custom BSDL file based on the .pin file for the test image. And you'll have to create a test step with a .jam file to load the FPGA before performing the boundary scan test.   Not pretty, but that's what you'll have to do if its too late to respin your FPGA I/O and copper ( ... as is the case with my team's project).   I have pasted below the response from Altera I got today on the matter ...       There has been an update to your Service Request, 10711323. Please go to http://www.altera.com/mysupport (http://www.altera.com/mysupport) to view the update. The following " To Customer " note was posted:   " Hi Jonathan, Sorry for the late response. We are currently testing on our device, and we observed that the output HIGH signal for these three pins are ~1.3V and output LOW signal are ~1.1V which are matched with your observation. While for other I/O pins, the HIGH signal is 1.9V and LOW signal is 0.5V. May I know what are the measurement for the other I/O pins from your side?   We have run the IBIS simulation with the maximum (16mA) and minimum (4mA) current strength. The HIGH signal for 16mA is ~2.3V and LOW signal is <0.5V. The HIGH signal for 4mA is ~1.8V and LOW signal is ~0.7V. It seems like the current strength for these three pins are lower than 4mA. We are still seeking for the reason behind. Meanwhile, could you please run the boundary scan test in post-configuration mode or reassign to other pins as a solution? I will update you once we have any update on the progress.   Thanks & regards, <name removed>