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4 GB SODIMM Bandwidth

Altera_Forum
Honored Contributor II
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Hi, 

 

How can I calculate the memory-bandwidth offered by a 4GB on-board SO-DIMM when I interface it with a Stratix EP3SL150 on a DE3 Board? 

 

Is this organized in 4 banks of 1GB? Can 1 controller access these banks, or would I need four controllers to maximize bandwidth? 

 

Thanks, 

~FPGAKitty~
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Altera_Forum
Honored Contributor II
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The available bandwidth from a DDR interface is determined by three things

  • The bitwidth (64 in your case) 

  • The memory clock frequency (around 400MHz) 

  • The access efficiency (in the 50% to 80% region)
Assuming burst accesses, without too much consideration for performance, then this would come out at 

 

Bandwidth (bits/sec) = 64 * 400 * 2 (for DDR) * 0.5 = about 25Gbit/s 

 

The number of banks is in the SODIMM datasheet, but the controller will correctly keep track of which ones are open.
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Altera_Forum
Honored Contributor II
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Thanks Cajun-Rat! 

 

One more question - how do we know the bit-width is 64 bit? [I risk sounding stupid] Is this FPGA-dependent? 

 

Thanks, 

~FPGAKitty~
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Altera_Forum
Honored Contributor II
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By 'bit width' I mean the number of DQ pins on the SO-DIMM module. All SODIMMs have either 64 or 72 DQ pins. The 72 pin wide modules are generally used with ECC. 

 

The only way to change this would be if you had a different Dev. Board, which might only have a single DDR2 chip and (say) 16 DQ pins. 

 

(DM and DQS/DQS# pins don't count as 'DQ pins')
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Altera_Forum
Honored Contributor II
864 Views

Hi, 

 

I am using a CycloneIII and I would like to use a 4B SODIMM (MT16HTS51264H). When I create the HDDDR2 controller in SOPC Builder I get the following error: 

 

Error: cpu_0: Memory map cannot fit within the addressable memory space of the Nios II Data Master which is restricted to 31 address bits 

 

How do I implement a SODIMM controller properly. do you have any idea what is going wrong? 

 

Thank you, 

Brianna
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Altera_Forum
Honored Contributor II
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As the error message suggests, the NIOS processor can only address 2GB (31-bit address bus).

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Altera_Forum
Honored Contributor II
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Thank you for the reply. When I change the DDR2 controller to interface w/ a 2GB sodimm I still get the same error. When I bring it down to 1GB then I'm alright. Does this mean I can only use a 1GB sodimm? I thought I saw other posts where people have successfully interfaced w/ at least 2GB.

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