Since you are asking in this forum I guess you are working with a FPGA or CPLD. Then you don't need any IC; simply instantiate a counter (at least 28bit wide) and reset it when it reaches 50'000'000. The reset signal will pulse at 1Hz frequency.Anyway, what's your purpose? Creating a 1Hz clock generally doesn't make sense: the common practice is using clocks in the MHz range and driving clock enable pins to get the proper switching rate.
If you want a a clock with a 50% duty cycle, then count to 50M/2 -> 25000000 and I sometimes use a clock in the <10 Hz range for signals like heartbeats, or well clocks (those that count seconds), so although it is uncommon it has its advantages (mainly in simulation time).