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5M160ZE64C5N --Minimum Solder voiding acceptance criteria in Thermal plane termination

5M160ZE64C5N.jpg

This criteria related to solder process of SMT(surface mount technology),  we would like to know the solder void of big thermal pad minimum acceptance criteria, the x-ray picture shows the solder voiding, but need INTEL technical team to identify this is acceptable or not? 

The component  used in Advanced Energy /ZENQ project.

Our designers use the thermal coefficient from the datasheet as the reference (example below), so requirement would be that the connection be similar to what the manufacturer used for the specification. However, it is unknown the standard that the manufacturer is using for installation of the device.

Could you help to advise:

1.Whats the standard/suggestion for the solder coverage for those big pads?

2.Any suggestion from them/your side to reduce voiding, any land-pattern design for those big thermal plane?

datasheet sample.jpg

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Hi,


Thank you for contacting Intel community.


Are you referring to process reflow for the FPGA? Kindly refer to

AN 353: SMT Board Assembly Process Recommendations for further info.


Let me know your feedback.


Thanks.


Regards,

Aiman


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Beginner
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Hi  Aiman,

The material package is QFP,  so we can refer to reflow process for QFP,

is it also applied for this recommendation? not sure if defines solder voiding acceptable criteria.

by the way, how to get this recommendation of AN 353?

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Hi,


Sorry that I missed out to put the link for AN353. Kindly go to the link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an353.pdf


Let me know your feedback after you have review the AN353.


Thanks.


Regards,

Aiman


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Hi,


If there is no further update on this request, i will continue to close this case.


Thanks.


Regards,

Aiman


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