8xPMA Direct Transceivers CMU PLL at 6Gbps failed

[Altera_Forum]

Hey everyone, 

 I was trying to use 8 channels (transmitter only) in PMA Direct mode with Stratix IV GX TR4 board (the device is GX230KF40C2). It worked fine at 4.8 Gbps, with CMU PLL.   However, when I tried to change the data rate to 6Gbps with CMU PLL, the error of 'x8 and xN Clock Line Timing Issue for Transceivers' occurred. Note that I have to use the output pins at HSMC_E port, therefore I can only use the top left two transceiver blocks, instead of the bottom left two. So, ATX PLL is not an option, because the device GX230KF40C2 doesn't have an ATX PLL in between the top left two transceiver blocks.   Even if I deleted pin assignment, it gave the same error at 6Gbps.  I also tried 6Gbps with ATX PLL without assigning the output pins, just to make sure my Quartus is working. And it was successful. However, the bottom left two transceiver blocks were automatically used.   According to the Errata sheet, https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/es/es_stratixiv_gx.pdf Basic (PMA Direct) xN should work at 6.5 Gbps for C2 speed grade with up to 17 channels. But I don't understand why Quartus doesn't like it. I am using Quartus 13.0sp1, I also tried the newest 15.0, still not working. So confused...  Thanks, Joel

[Altera_Forum]

Just wonder if you do not put any pin location assignment, select CMU PLL, will the Fitter pass compilation?

[Altera_Forum]

--- Quote Start ---  Just wonder if you do not put any pin location assignment, select CMU PLL, will the Fitter pass compilation?  --- Quote End ---    I tried that as well, and the Fitter didn't pass. Thanks for pointing it out; I added this note in the main post.

[Altera_Forum]

Since you have tried quite a number of options, probably you might want to contact your FAE to seek further assistance or file a case to Altera to see if there is any limitation.