Cyclone V fitter cannot place fractional PLL

[Altera_Forum]

Hi All! 

 Right now I'm trying to compile the simple design to check if pin assignment is correct before I start to route the PCB. In our project we use 8 ADCs (output interface of each ADC is 9xDATA LVDS, 1xDCLK). I generated 8 deserializers (ALTLVDS_RX) in order to deserialize the incoming data from 8 ADCs. Then I use fifo and internal memory. The rest of the project is missing yet. As I mentioned earlier the main goal of this project is to see if the pin assignment is correct and if the fitter is able to place all the deserializers in the FPGA.  After I prepared the project I wanted to compile it but unfortunately the fitter cannot place the fractional PLL. I tried different pin locations but the compiler still cannot put the design into the FPGA.  As the Cyclone V 5CEBA9F27C7N has 8 PLLs and 84 true-lvds receivers I thought that I would be able to fit the design with 8 deserializers (80x LVDS inputs).  Now my question is: if the fitter cannot fit the pll, is there anything else I can do about that? Or simply I have to look for another FPGA?  Best regards and thank you in advance, K

[Altera_Forum]

Have you tried compiling the project without any pin assignments? Based on what you've presented I would anticipate a solution being available. However, it may be that the assignments you've already made are preventing Quartus from finding a fit for your design. 

 Regards, Alex

[Altera_Forum]

--- Quote Start ---  Have you tried compiling the project without any pin assignments? Based on what you've presented I would anticipate a solution being available. However, it may be that the assignments you've already made are preventing Quartus from finding a fit for your design.  Regards, Alex  --- Quote End ---    Yes, I tried to compile the design with no pins assigned and the fitter also wasn't able to fit the design into the FPGA.   Regards, K

[Altera_Forum]

Have you tried to cascade two fPLL?. Set the output of the first one as the input of the second one, which should be the transceiver's PLL. I found the same problem using the cycloneV development board and I overcome the problem doing that. 

 Luck.

[Altera_Forum]

When the fitter fails, when you run it without any pin assignments, what are the errors it fails with? Do you still have the problem? If not, do post the solution... 

 Cheers, Alex

[Altera_Forum]

--- Quote Start ---  Have you tried to cascade two fPLL?. Set the output of the first one as the input of the second one, which should be the transceiver's PLL. I found the same problem using the cycloneV development board and I overcome the problem doing that.  Luck.  --- Quote End ---    Can you tell me how to deal with it using transceiver's pll? How to cascade two fpll?

[Altera_Forum]

--- Quote Start ---  Hi All!  Right now I'm trying to compile the simple design to check if pin assignment is correct before I start to route the PCB. In our project we use 8 ADCs (output interface of each ADC is 9xDATA LVDS, 1xDCLK). I generated 8 deserializers (ALTLVDS_RX) in order to deserialize the incoming data from 8 ADCs. Then I use fifo and internal memory. The rest of the project is missing yet. As I mentioned earlier the main goal of this project is to see if the pin assignment is correct and if the fitter is able to place all the deserializers in the FPGA.  After I prepared the project I wanted to compile it but unfortunately the fitter cannot place the fractional PLL. I tried different pin locations but the compiler still cannot put the design into the FPGA.  As the Cyclone V 5CEBA9F27C7N has 8 PLLs and 84 true-lvds receivers I thought that I would be able to fit the design with 8 deserializers (80x LVDS inputs).  Now my question is: if the fitter cannot fit the pll, is there anything else I can do about that? Or simply I have to look for another FPGA?  Best regards and thank you in advance, K  --- Quote End ---    Hi,  Based on your description, it seems like each deserializer is consist of 10 LVDS RX pairs. Since without user pin assignment, Fitter also trigger error, this might due to limited resource to implement your design. Just wonder if you have tried by starting your design with lesser LVDS channels to see if it work? Ideally you can start by placing one channel then slowly add on.

[Altera_Forum]

Agree with bfkstimchan, starting with simple test design would definitely ease the cause debugging.