A mistake in the Strarix IV handbook ? (duty-cycle at PLL input).

[Altera_Forum]

Hello all, 

 The FPGA I'm working on is a Stratix IV GX, assembled on a board designed in my company. The board contains a 148.5MHz 3.3V clock oscillator, which drives a dedicated clock input pin of the FPGA. This dedicated clock input pin drives an FPGA-internal PLL (altpll). The parameters of this internal PLL are: N modulus (frequency divider, whose input is the dedicated clock pin, and output drives the PFD reference input) = 11. M modulus (frequency divider, whose input is the VCO , and output drives the PFD feedback input) = 40. C modulus (frequency divider, whose input is the VCO , and output drives the altpll output ) = 5. To summarize in a nutshell, my PLL is thus: 148.5MHz x (1/11) x 40 x (1/5) = 108MHz.  (VCO operates at 148.5MHz x (1/11) x 40 x 2 = 1080MHz since it has a "/2" post-scale).  Both FPGA's handbook and Altera FAEs whom I talked to, insist that the duty-cycle at the clock input pin driving a PLL should be 40%-60% or better. I understand that the PFD may not operate correctly at duty-cycles worse than 40%-60%. Since I'm not a PLL expert, I respect Altera's position that PFD needs at least 40%-60%. However, I do not understand, why should the clock input pin need at least 40%-60% as well.  **under the assumption**, that my 148.5MHz clock meets the tHIGHmin and tLOWmin at the FPGA dedicated clock input, it seems the duty-cycle of the clock at the PFD reference input is always 5/11= 45%, since N modulus is 11, and this is regardless of the 148.5MHz duty-cycle. My questions are infact very simple: 1. what is the actual duty-cycle at pfd reference input ? is it not always 45% ? 2. why should the 148.5mhz meet the 40-60% duty-cycle constraint, assuming pfd always "sees" 45%, and assuming the 148.5mhz also meets the thighmin and tlowmin constraints ? 3. can it be that the 40%-60% clock input constraint listed in the handbook, is an over-kill (unless of course, if the n modulus is 1) ?    Thanks