AC Coupled LVDS vs DC Coupled LVDS

[Altera_Forum]

Hello to everyone, 

 this time I´m coming to you with a question regarding the kind of coupling between the development board and the external devices where one would like to read or write data. In my design I am using a Terasic TR4 development board, based on Stratix IV EP4SGX530KH40C2, with 6 HSMC connectors, some of them containing pins for true LVDS transmitters and receivers at 1.6Gbps.  I am trying to interface this with a TI TSW30SH84 Evaluation module, and I have now a doubt about the coupling between the two board. Reading the TSW30SH84EVM manual, I have found out that I have the possibility to read the internally generated clock signal of the DAC board (737,28 MHz) out of the HSMC connector, and use it inside my design for example to generate the necessary clocks in order to send the data back to this board. In my case I may need to generate a SYNC signal and the DATA CLOCK in order to send the data to the DAC. Looking at the TSW manual, I have seen that the clock signal coming out of the board is delivered to the HSMC connector as AC-COUPLED LVDS.   The first question is: As I know that this EVM should be directly compatible with Altera FPGA boards, does it represent a problem this kind of coupling for such a signal? I was reading that the AC coupling, for high speed applications, is recomended just for DC balanced signals, and this should be the case as we are talking about a 50% duty-cycle clock signal. Actually if I try to forward the clock signal feeded inside the HSMC connector, on an SMA in order to measure it on an oscilloscope, I see it with the right frequency, but I am wondering if I will face some other problems.  The second question is: When I need to send a differential clock signal to my DAC board, the standard accepted from it is DC coupled LVDS. Is this the normal way LVDS signals are handled on Altera HSMC connectors?  If someone could tell me if I´m operating correctly, or how can I take care about the possible issues would be great.  Greets,  Giovanni

[Altera_Forum]

AC and DC coupling of differential signals is discussed in these app notes: 

 http://www.ti.com/lit/an/scaa059c/scaa059c.pdf http://www.ti.com/lit/an/scaa062/scaa062.pdf https://www.idt.com/document/apn/lvds-pecl-termination-app-note  In your case, AC-coupling or DC-coupling clock-like signals is fine.  If the data lanes are AC-coupled, then those lanes would need to be modulated so that have no DC-disparity, either by a PRBS pattern or by 8/10B encoding.  Cheers, Dave

[Altera_Forum]

The other requirement is that the inputs must have DC bias networks. The FPGA LVDS inputs don't have it, I think. So you have to bias to 1.2V externally.