AC coupled LVDS clock input - Stratix V

[Altera_Forum]

Hello,  

 We are using one of the CLK inputs (not REFCLK) of our 5SGSMD5K2F40I2LN device as an LVDS receiver of a 54MHz clock.  Currently our clock is ac coupled to the input (as illustrated below) and the internal 100 ohm termination is used.   http://www.alteraforum.com/forum/attachment.php?attachmentid=11975&stc=1   Although this seems to be working, I'm a bit concerned since I couldn't find any mention of internal biasing of LVDS inputs and the only diagram in the LVDS termination section is of an DC coupled connection.  http://www.alteraforum.com/forum/attachment.php?attachmentid=11970&stc=1   So, my questions are:  Is the ac coupled connection shown above legal?  If so, do I have to provide external biasing or is there internal biasing that can be used?   Thank you in advance,  Alex

[Altera_Forum]

The table I attached I took from the Stratix V datasheet found here: https://www.altera.com/en_us/pdfs/literature/hb/stratix-v/stx5_53001.pdf 

 I guess VICM is input common mode voltage, and for data rates below 700Mbps it should range from 0.05V to 1.8V, so maybe AC-coupling it will be ok?    http://www.alteraforum.com/forum/attachment.php?attachmentid=11976&stc=1

[Altera_Forum]

Table 22 (page 16) in Stratix V Device Datasheet (https://www.altera.com/en_us/pdfs/literature/hb/stratix-v/stx5_53001.pdf) has Differential IO Standard Specifications. 

 For data rates below 700Mbps the VICM(DC) range is 0.05V to 1.8V, and for data rates above 700Mbps it is 1.05V to 1.55V. Note 1 says: For optimized LVDS receiver performance, the receiver voltage input range must be between 1.0V to 1.6V for data rates above 700 Mbps, and 0 V to 1.85V for data rates below 700 Mbps.  The glossary on page 68 has the following definitions: VCM(DC) - DC common mode input voltage. VICM - Input common mode voltage—The common mode of the differential signal at the receiver.   To be honest, I find it very confusing. Is VICM(DC), VCM(DC) and VICM all the same, or are they not? On one hand, it seems like the datasheet is saying that the common mode can go (almost) to 0V, and a true differential signal swinging around 0V has 0V common mode, so if that's the case then it should be ok. But I'm not very convinced about it, I have a suspicion that what they mean is the LVDS input's DC range is from 0V to 1.8V (note 1), and the input should not go below 0V, in which case it would probably not be ok to AC-couple the signal.  Lets see what others are saying. Some people have asked similar questions before:  http://www.alteraforum.com/forum/showthread.php?t=47998 http://www.alteraforum.com/forum/showthread.php?t=36578 http://www.alteraforum.com/forum/showthread.php?t=42008  This guy probably has the best answer: http://www.alteraforum.com/forum/showthread.php?t=36578&p=150967#post150967  So it seems like if the common mode output from the clock driver matches the common mode input of the receiver, then DC couple is probably best. If not, and you have to AC couple, you should probably add the resistive divider to get the right DC bias at the receiver inputs.

[Altera_Forum]

See Altera's "do lvds receivers in altera devices have on-chip dc-biasing resistors? (do lvds receivers in altera devices have on-chip dc-biasing resistors?)" support solution. It confirms there are no biasing resistors inside the devices. 

 Perhaps also look at TI's "ac-coupling between differential lvpecl, lvds, hstl and cml (https://www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahukewjc5spj88flahvlcj4khatfaowqfggcmaa&url=http%3a%2f%2fwww.ti.com%2fcn%2flit%2fpdf%2fscaa059&usg=afqjcnfvvvaqdq2md_2ebflend_y9puhlw&bvm=bv.117218890,d.bgs)". This covers your case and suggests some biasing solutions.  Cheers, Alex