Hello guys,
Does somebody know how to setup the ACP port so I can use a FPGA master to access the SDRAM data with cache coherency?
I have a FPGA module which does something like a DMA transfer, I have it working by using the FPGA-SDRAM ports, but I would like to use the FPGA-HPS with the ACP port.
Someone told me to pass the RAM physical address of the data I want to handle "| 0x80000000" so I can access the ACP window, but after doing that I got a kernel panic,
I am not sure if I need to do some initial setup for that ACP port, the FPGA master module is connected via the FPGA-HPS bridge and I have changed the AW[AR] Cache attributes of the AXI port to enable the cache for both writes and reads.
I have a DE1-SoC boad, with Linux 3.10 LTSI, it was built using Yocto and a guide from rocketboards.org.
I am using some ideas from the project:
http://rocketboards.org/foswiki/view/projects/datamover. There is an axi_conduit_merger module which allowed me to changes the AXI attributes from the Linux application.
Not sure what I am missing.
Any help would be appreciated.
Thanks.
