AGFB023R25A external loopback 53.125Gbps PRBS checker error after initial adaptation

[jason_chen8310]

Hardware board: AGFB023R25A Ethernet Card + 100G QSFP28 DAC cable external loopback.

Problem:  Use the System Debugginng Toolkits com-altera-systemconsole-app-shell to debug 53.125Gbps performance. Serial Loopback is ok ( ber=0 and inject error bits is tested ok). But  BER is wrong when set to external loopback ( The message is "Hard PRBS checker error counter has saturated and checker is stopped accordingly...,  But the lock status is True and ber is showing continuely when I turn the adaptation mode to continous Adaptation).

Question: Please help me check the Serdes of FPGA setting. Now I can't see any of serdes setting on this console toolkits.

Note: hardware is ok, cable is ok , test operation procedure is OK. The BER result is OK when I tested 2 days before. 

[Yi]

Hi Jason,

How long is your external loopback module? Firstly I'd like to suggest you try to add a bit TX EQ see if the link would be better first, just in the lower part of the Tx channel parameters.

[WZ2]

Hi there,

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