AGILEX 7-I R-Tile PCIe Root port : Unsupported Request received after enumeration

[Serge93]

hello,

I am using the the Agilex 7-I r-tile Dev kit board in PCIe Root Port.

After I have done my enumaration when I am doing a Memory Read of one 32-Bits data, I receive a completion with 'Unsupported Request'.

Is my Enumeration bad ?

Thank you.

Serge

[RongYuan]

Hi,

Please check the link status is OK before doing a mem read/write.

Please confirm the PCIe Command Register bit 1 is set and also confirm the address you read is valid.

Regards,

Rong

[Serge93]

Hello Rong,

Thank you to come back to me.

1) Yes the Link up is stable and good.

2) Can you detail what you mean by the PCIe Command Register ? What address ? in Root Port or in Target ?

3) Yes the address is fully valid in the Target.

Please find attached the Signal Tap of all the Enumeration sequence done from the AGILEX 7-I R-Tile Root port and then the Memory Read done at the end on the Target with the Unsupported Resquest Completion received.

This way you can verify easily what I am doing wrong.

Thank you for your help.

Serge

[RongYuan]

2) Can you detail what you mean by the PCIe Command Register ? What address ? in Root Port or in Target ?

-->PCIe configuration space offset 0x4. Check RP side. Bit 1 is for Memory Space Enable.

Regards,

Rong

[Serge93]

Hello Rong,

Yes Bit 1 and Bit 2 are set to 1.

Have you read the Signal Tap I sent you ?

Thanks.
Serge

[RongYuan]

Hi Serge,

Not sure I understand those signals. You're using Gen2 x2 and rx_st0_hdr_int data is not correct, is that your question?

Regards,

Rong

[Serge93]

Hello Rong,

Which signals do you not understand ?

The PCIe configuration is Gen3x4.

The following signals :

slow_clk                   

slow_clk_resetn

avs_reconfig_address(31:0)     

avs_reconfig_read          

avs_reconfig_readdata(7:0)    

avs_reconfig_readdatavalid

avs_reconfig_write       

avs_reconfig_writedata(7:0)   

avs_reconfig_waitrequest 

enable to configure registers in the PCIe IP configured as a Root por, mainly for PCIe Enumeration.

The following signals :

Tx_st0_sop

Tx_st0_eop

Tx_st0_hvalid

Tx_st0_hdr(127:0)

Tx_st0_dvalid  

Tx_st0_data(127:0)

Tx_st1_sop

Tx_st1_eop

Tx_st1_hvalid

Tx_st1_hdr(127:0)

Tx_st1_dvalid

Tx_st1_data(127:0)

Tx_ready

Enable to send PCIe commands to the PCIe Target (SSD) ( config Write, config Read, Memory write, Memeory read, etc..)

The following signals :

Rx_st0_sop

Rx_st0_eop

Rx_st0_hvalid

Rx_st0_hdr(127:0)

Rx_st0_dvalid

Rx_st0_data(127:0)

Rx_st0_empty(1:0)

Rx_st1_sop

Rx_st1_eop

Rx_st1_hvalid 

Rx_st1_hdr(127:0)

Rx_st1_dvalid

Rx_st1_data(127:0)

Rx_st1_empty(1:0)

Enables to receive PCIe commands from the PCIe Target (SSD) ( Completion with or without data, Memory write, Memeory read, etc..)

My question is :

What is wrong in my command sequence to get an unsupported request on the first read after my PCIe enumeration ?

Or, do I miss something to do ?

To answer to this question, you need to analyze my signal tap, on which you have all the accesses recorded included the Unsupoorted Request Completion.

On my side I do not see what is wrong.

Thanks for help.
Serge

[RongYuan]

Thanks for the info.

From the RP side, please read config addr 0x10 to see if the bit0 is 0.

Regards,

Rong

[Serge93]

Hello Rong,

The reading of the address 10h (BAR0) in the Agilex 7 PCIe RP is equal to 00h.

Can you check this write access :

It is supposed to be a Memory Write at address 40000014h of 1DW with the value 00460000h

The Completion is an Error Message IRQ code 31h :

Thank you.
Serge

[RongYuan]

It looks a mem bar is enabled for use. Somehow the config addr 0x20-27 data does not look right. Normally in a cpu-based test, a mem wr always has a requester id in hdr.

If possible, my suggestion is to set a fpga pcie endpoint design, check the root port parameters from lspci. You may confirm the address base and limit for the device is correct before using it.

Regards,

Rong

[Serge93]

Hello Rong,

The requester ID is fixed in hardware by the R-Tile PCIe IP, you cannot modify it.

I have configured the Memory Base and Limit but not the prefectchabel one.

Knowing I do not want Prefetch access...

Sorry I cannot do your suggestion.

Thank you.
Serge

[RongYuan]

From your stp, the mem read addr is 0x14000040 which seems not the device bar addr 0x40000004. Please check this.

Regards,

Rong

[Serge93]

Hello Rong,

In that case everything in my Header has to be revert, not only the address...

Can you confirm me the mapping of the Header which is not very clear in the ug20316 page 73-74.

R-Tile is configured with the ' PCIe Header format' enabled :

Can you confirm me the mapping to use with the following signals :

  st0_hdr(31:0) <= 01000040h                                                     – Memory write 32-Bits command=40h, Length=(7:0)=01h => 1DW 

  st0_hdr(63:32) <= 0Fh & 000PORT_TAG_NB(5:0) & 0000h - TAG, LAST_BE=0h, First_BE=Fh, Requester_ID=0h

  st0_hdr(95:64) <= (BASE_ADD_EP + 14h) – Add Reg            – Address(31:0)

  st0_hdr(127:96) <= 00000000h                                                - Reserved

If this mapping is not correct please write the correct one.

Thank you.
Serge

[RongYuan]

For mem write, the hdr in stp would likely to be

0x40000001_0000000F_40000014_00000000

Regards,

Rong

[Serge93]

Hello Rong,

Thank you it solved the problem.

Thank you very much for your help.

You can close the case.

Serge