AGILEX5 - HPS-first - timeout waiting for RECONFIG_COMPLETED

[MM-ATH]

Hello,

I am using HPS-first boot scheme on AGILEX5 AXE5-Eagle dev board. I have suddenly problem with writing FPGA (fpga_core.rbf) from running linux. Before it worked as expected, but now I am getting these errors:

[   39.349511] fpga_manager fpga0: writing /images/fpga_core.rbf to Stratix10 SOC FPGA Manager
[   46.563143] Stratix10 SoC FPGA manager soc@0:firmware:svc:fpga-mgr: timeout waiting for RECONFIG_COMPLETED
[   74.235126] svc_thread_cmd_config_status: poll status timeout
[   74.240952] fpga_manager fpga0: Error after writing image data to FPGA
[   74.247993] fpga_region region0: failed to load FPGA image
[   74.253484] OF: overlay: overlay changeset pre-apply notifier error -110, target: /soc@0/base_fpga_region
[   74.263055] create_overlay: Failed to create overlay (err=-110)

The same fpga_core.rbf image can be written without issues from u-boot. I have older fpga_core.rbf which can be written also from linux. Recent changes in fpga_core.rbf design were mailnly in experimenting about EMIF in FPGA-connected RAM (not HPS-one). I have tried multiple compilations and present compilations can not be written from linux, only from uboot.

This is my overlay.dts

/dts-v1/;
/plugin/;
/ {
  fragment@0 {
    target-path = "/soc@0/base_fpga_region";
    __overlay__ {
      firmware-name = "/images/fpga_core.rbf";
      config-complete-timeout-us = <10000000>;
    };
  };
};

Should I fiddle with some timeouts somehow?

Loading FPGA from u-boot takes about 1-2 seconds max.

[MM-ATH]

Yesterday at least two compilations couldn't be loaded, today two compilations can be loaded to FPGA correctly also in linux. So maybe problem disappeared.

[MM-ATH]

Problem remains, 

some compilations can be loaded in linux, some not (all of them can be loaded in u-boot).

[Jeet14]

Hi,

Is this issue still there?

Which Quartus version you are using for old .rbf and new .rbf?

Also, mention the uboot, ATF and kernel versions used?

Regards

Tiwari

[MM-ATH]

Hi Tiwari,

yes, issue is still there, Quartus version is 24.3.1 Build102 01/14/2025 (Patches none).

Regards

Martin

[MM-ATH]

Hi Tiwari,

yes, issue is still there,

Sometimes there is also this error (this design can be programmed also in u-boot):

[    8.577797] fpga_manager fpga0: writing /images/fpga_core.rbf to Stratix10 SOC FPGA Manager
[   11.120096] svc_normal_to_secure_thread: STATUS_ERROR
[   11.125195] Stratix10 SoC FPGA manager soc@0:firmware:svc:fpga-mgr: ERROR - giving up - SVC_STATUS_ERROR
[   11.134790] fpga_manager fpga0: Error after writing image data to FPGA
[   11.141815] fpga_region region0: failed to load FPGA image
[   11.147394] OF: overlay: overlay changeset pre-apply notifier error -14, target: /soc@0/base_fpga_region
[   11.156908] create_overlay: Failed to create overlay (err=-14)

Quartus version is 24.3.1 Build102 01/14/2025 no patches.

Regards

Martin

[MM-ATH]

We removed F2HPS bridge from design (we don't need it, it was relict of GHRD design), due debuging of Other problem and since then all designs can be programmed also in linux via dt-overlay (about 7 compilations now).

[MM-ATH]

I am sorry, I forgot to write other versions, so here they are:

kernel is 6.6.37 - 6.6.37-ge98c5f87520c

ATF is 2.11.0 - BL31: v2.11.0(release):QPDS24.3_REL_GSRD_PR

u-boot is U-Boot SPL 2024.04-35103-gdc428c3751

[MM-ATH]

After we updated Quartus from 24.3 to 25.1 version, we are getting this error, if we try to programm design.core.rbf from linux via dt-overlay.

[   15.843462] Stratix10 SoC FPGA manager soc@0:firmware:svc:fpga-mgr: timeout waiting for svc layer buffers

Same design.core.rbf worked with first stage loader from Q24.3. We programmed it from LINUX first with FSBL from Q24.3 succesfully, and then programm QSPI NOR flash with the newly generated design_jic.rpd. After reboot we see that error, if we try to programm design.core.rbf as before.

[JingyangTeh_Altera]

Hi

Sorry for the late reponse.

Jeetesh is OOO and I will be helping out with the case.

Could you try the overlay file changes below:

/dts-v1/;

/plugin/;

/ {

fragment@0 {

target-path = "/soc/base_fpga_region";

#address-cells = <2>;

#size-cells = <2>;

__overlay__ {

#address-cells = <2>;

#size-cells = <2>;

firmware-name = "fpga_core.rbf";

config-complete-timeout-us = <30000000>;

};

Regards

Jingyang, Teh

};

};

[JingyangTeh_Altera]

Hi

Do you have an update on this case?

Did you tried out the suggestion from the previous comment?

Regards

Jingyang, Teh

[MM-ATH]

Hi Jingyang,

I am sorry, not yet. 

Because of potponed availability of AGILEX5 chips of size and price we wanted, I am now working on EFINIX devkit to have some parallel way, if chips would not be available in time we want...

Martin

[JingyangTeh_Altera]

Hi

In that case, could we close this case first and create a new one once you are working on this issue again?

Regards

Jingyang, Teh

[MM-ATH]

OK,

thanks for your support.

Martin

[JingyangTeh_Altera]

Hi

I will now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh