[AHDL] Problem with MUX

Altera_Forum · ‎12-07-2009

I am a newbie to Quartus and AHDL. I have problem with multiplexer 3 in 1 out. When I simulate I get for 0 and 1 signal A, for 2 signal B, for 3 signal C.


SUBDESIGN mux_3_8bit_1
(
    A, B, C        : INPUT;    -- wejscia 8 bitowe - sygnaly w kodzie BCD
    s                            : INPUT;    -- sygnaly sterujace
    Y                            : OUTPUT;    -- sygnal wyjsciowy
)
BEGIN
    CASE s IS
        WHEN 0 =>    Y = A;
        WHEN 1 =>    Y = B;
        WHEN 2 =>    Y = C;
        WHEN 3 =>    Y = B"00000000";
    END CASE;
END;

Maybe someone culd help me?

Altera_Forum · ‎12-07-2009

Looks ok to mean - you sure its not a problem elsewhere?

Other than that - Id recommend not using AHDL anymore. Move to VHDL or Verilog instead. AHDL simulation is only supported in the quartus simulator, which wont exist for new versions of quartus.

Altera_Forum · ‎12-07-2009

I must use AHDL, because this is requirment of project.

During simulation i get a lot of warning. for example:

--- Quote Start ---

Warning: Found glitch at time 0.5 ns of duration 0.5 ns on node "|mux_3_8bit_1|A[0]"

...

--- Quote End ---

Altera_Forum · ‎12-07-2009

Exolten-one, you probably have glitch-detect turned on. See Assignments->Settings-->Simulation Verification

Tricky, you do mean that the Quartus internal simulator is going to disappear?

Altera_Forum · ‎12-07-2009

josyb, You are right. When I turne off glitch-detect warnings disapear, but timings are shifted.

Altera_Forum · ‎12-07-2009

This is what I simulated, looks very plausible to me

Altera_Forum · ‎12-07-2009

In my simulation looks that

Thanks all for help. Problem concerned project. When I make new project problem have disapered.