AHDL equivalent to Preserve in in Verilog

[Altera_Forum]

Hi  

I am migrating an existing AHL design from MaxPlus to Quartus environment and I noticed that some of the state machine's states/registers were optimized out.  I know that in Verilog, Preserve attribute can be used. Does AHDL has similar/equivalent attributes?   Thanks Alan

[Altera_Forum]

If they were optimised out, there is probably a reason. It wont have anything to do with the language.  

I dont know of attributes in AHDL, but you can provide similar attributes directly to registers in the global assignments settings in the project (I dont know about this for Max Plus)  Also remember that the synthesisor is improved since max plus 2, so may behave differently. I have had MaxPlus compile things for me that quartus says are illegal.  My Guess is poor design in the AHDL combined with a better synthesisor.

[Altera_Forum]

PS. Quartus will synthesis AHDL just fine - why the language migration? you are adding a risk of the two not being the same.

[Altera_Forum]

Hi 

 Below is the piece of SM in AHDL    base_2 :MACHINE WITH STATES (s0_ base_2,  s1_ base_2,  s2_ base_2,  s3_ base_2);    int_ff2.clk = h1; int_ff2.d = zoom_a;   base_2.clk = !h1;   CASE ( base_2) IS   WHEN s0_ base_2 => /int2 = vcc;  IF int_ff2.q THEN base_2 = s1_ base_2;  ELSE base_2 = s0_ base_2;  END IF;   WHEN s1_ base_2 => /int2 = gnd;  base_2 = s2_ base_2;   WHEN s2_ base_2 => /int2 = gnd;  base_2 = s3_ base_2;   WHEN s3_ base_2 => /int2 = vcc;  IF int_ff2.q THEN base_2 = s3_ base_2;  ELSE base_2 = s0_ base_2;  END IF;  END CASE;   In Quartus simulation, I could not locate "s2_ base_2" , the warning message was   Warning: Can't display state machine states -- register holding state machine bit "s2_base_2" was synthesized away

[Altera_Forum]

The Quartus software manual tells about HDL synthesis directives  

  --- Quote Start ---  The AHDL language does not support the synthesis directives or attributes described in this chapter.  --- Quote End ---   Sounds like tcl commands respectively settings in the Quartus assignment editor are the only means to achieve what you want.

[Altera_Forum]

Do you have sample of tcl command to achieve this?

[Altera_Forum]

Figured out from *.vqm file that these nodes were renamed by quatus when logic packing happens ( ie combining com & registered function ) in a single LE.  

for "s2_base_2" , the new name is s2_base_2~20 ( for registered output )  Can anybody help with tcl command to preserve the node coz it will help me . Thanks

[Altera_Forum]

According to the AHDL manul from 1995 you should be able to use the LCELL for combinatorial logic. It's not optimized away during the logic synthesis. But I'm not sure about the name - guessing it still can be changed.

[Altera_Forum]

it cannot be fuly defined state-machine . you must provide 'reset' signal 

also there are rules how to write code so synthesis tool aware state-machine. you can make statemachine through TRUTH_TABLE in AHDL. it is only one operator that missed in VHDL.

[Altera_Forum]

i guess one shoud check if code complies the recomendations "how to..."

[Altera_Forum]

or you can use Assignment Editor after Analysis and Elaboration stage. open assignment editor in Assignments menu look for you node in Node Finder in field TO (generally) make assignment for register or if it is really state-machine you can assign type of state-bits encoding

[Altera_Forum]

There is no requirement for a reset in a state machine. An initial value is good enough.

[Altera_Forum]

perhaps Tricky, you are right. but if you look better in code you find that there are 2 edges of clock instead of 1.  

I don't like such bad time shifting that decrease setup times for outputs. Then i suggest one (AlanIsmail) should open MAxPlus help file and read carefully about coding style for AHDL.