ALT2GXB on CYCLONE IV GX

[Altera_Forum]

Hi every one! 

 I'm a newbie about the GXB transceivers.  I'm trying to realize a transmission channel very simple using a Cyclone IV GX(EP4CGX15BF14C8N.  ) device on a board realized in my company.  In order to test it actually i check if the PLL of the transmitter locks the pll_inclk[0].  I connected the Clock generator to the pin E7 (pll_inclk[0]) . but not in differential mode.  (PIN E6 connected to ground)  Note that the "normal" pll locks to the frequency. (100MHz)  I made a considerable numbers of attempts, but up to now i was not able to use it.  What could be the main problem? -The clock that is not differential? -The tranceiver needs a different clock respect to the "FPGA fabric ?" -or both? Best regards. PS: I have a very similar issue on a Stratix II GX Based Board.

[Altera_Forum]

Hi, 

 Your post does not state what is the result you get, and what you'd expect. Also you do not describe your setup detailed enough.  Anyway, I had a strange GX problem with Cyclone IV GX. I instantiated an RX-only GX unit. I did follow the reset sequence recommendation, but could not see freqlocked signal to activate. Finally I found out that if I instantiate TXRX GX and do not use TX path at all, the freqlocked signal behaved as documented.  If I remember correctly, Altera documentation says that diff-clk is mandatory if using GX blocks. You could probably tie one pin to ground through capacitor, or tie it to a voltage which is middle of input voltage swing. But the jitter performance might suffer. If you connect the negative pin to ground, you can not configure the input *** diff (the positive input can never have voltage smaller than negative input).  BR, -Topi

[Altera_Forum]

Thank you very much for the reply. 

I'm sorry for the few clarity I'll try to amend in the following   I connected the Clock generator to the pin E7 and the PIN E6 to ground and i configured the PIN E7 as 2.5V (IO Standard)  I configured the GXB transceiver just as transmitter (protocol BASIC, without 8b/10B)  The inputs for the transceiver are - tx_datain[9..0] connected to a lpm_constant -pll_inclk[0] connected to E7  -cal_blk_clk (connected to E7)  The clock generator has a frequency of 100 Mhz  The outputs of the TX transceiver are:  tx_dataout[] pll_locked[0] tx_clockout[0]  The expected result is that the pll_locked Signal goes to "High" Level  But i did not get it  As i already mentioned, unsing a normal PLL (altpll Megafunction) and using the same clock the pll_locked signal goes in "HIGH" state.   I made this test because, looking at the netlist using "Resource Property Editor"tool in QuartusII i saw that the PLL of the transceiver is a separated entity of the transceiver  and it seems that is the same of the ALTPLL megafunction  and both are connected to the output pll_locked in the same way.  Thank you for the hint. I'll try to instantiate also the RX channel.  About the diff-clk: I searched in the handbook of the Cyclone IV and in the Guidelines for the connection of the pins, but i did not find anything of mandatory   It could be very useful if you could indicate me where i can find this sentence.  Thanks a lot again  Best Regards

[Altera_Forum]

Dear All, 

i found that the clock has to be differential in the Knowledge BAse of Altera. (Solution ID: rd05032011_649)  Please note that the fitter (quartus 12.1) does not give any error.  Best Regards