ALTCLKCTRL en signal

Altera_Forum · ‎12-17-2015

Hi

for cyclone iv e

I want to generate a gated clk for ADC with ALTCLKCTRL :

1 clk in and 1b en.

is it possible that the en signal will be timed (generated) with the same clock that being gated with no race?

thanks

Yotam

Altera_Forum · ‎12-18-2015

You can't use logic in that gated domain to drive the enable, because once it's off it's off. I believe there is an option to synchronize the enable signal, whereby it adds flip-flops and it is designed to turn off/on glitch free. It can be synchronously timed too, so you could have another clock coming out of the same PLL that is not gated and drives this. I've created some circuits like that for others(although I didn't fully test them or hear back on what exactly happened). I believe you can turn it on/off within the next clock cycle that way. (Be sure to run TimeQuest and make sure that path to the enable is analyzed.)