ALTDDIO Megafunction question

[Altera_Forum]

Hi all! 

 I'm working with ALTDDIO megafunction. I use DE2-115 Dev Board which means Cyclone IV is an FPGA I'm dealing with.   As I understand then I use ALTDDIO_IN Quartus should implement two registers, one negative edge and one rising edge,  also should be a latch for synchronizing data. But in manual (http://www.altera.com/literature/ug/ug_altddio.pdf) on page 15 I see text "... IOE configured for DDR inputs" which I think means that functionality of DDIO should be implemented using I/O resourses.  My test project contains LVDS_RX input and ALTDDIO mf. In Chip Planner I see that two registers implemented not in I/O Pads, but using FPGA inner resourses, LABs. In resourse property editor I see that DDIO mode parameter value set to "none".  My first question is why it's not implemented in IO. Secondly, what should I do, only create own atoms or there is another way to use I/O resourses?   I also tried to set the default assignment of input pin - 2.5 V, not LVDS.

[Altera_Forum]

Cyclone IV doesn't have dedicated DDR input registers. Review the DDR Input Registers paragraph in the device manual.

[Altera_Forum]

Thank's a lot, FvM!! 

 Actually that info exists in handbook.   I was bluffed by the ability of creating own atoms, because in that case I thought I can use DDIO device resourses in input mode.  But as I realize in Cyclone IV DDIO implemented in I/O element registers only if I use DDIO_output mf, there is no dedicated I/O resourses for input data.  The only question is why such inequality take place.

[Altera_Forum]

Apparently the DDR output function which also involves output enable registers is more critical.

[Altera_Forum]

Many thanks, FvM!!!